三维集成电路堆叠硅通孔动态功耗优化

三维集成电路堆叠硅通孔结构具有良好的温度和热特性. 提出了一种协同考虑延时、面积与最小孔径的堆叠硅通孔动态功耗优化办法. 在提取单根硅通孔寄生电学参数的基础上, 分析了硅通孔的直径对多层硅通孔的功耗与延时性能的影响, 由此构建了分层逐级缩减堆叠硅通孔结构, 分析了硅通孔高度与氧化层厚度的影响. 结果表明, 该模型可在牺牲少许延时的情况下显著优化动态功耗, 在允许牺牲延时5%的情况下, 堆叠硅通孔的动态功耗最多可减少19.52%.

Stack-through silicon via dynamic p ower consumption optimization in three-dimensional integrated circuit

Stack-through silicon via (TSV) used in three-dimensional integrated circuit has good temperature and heat transfer characteristics. A novel model for optimizing the dynamic power consumption based on stacked-TSV is proposed in this paper, in which delay, area and minimum aperture are comprehensively considered. After extracting single TSV parasitic electrical parameters, we analyze the influences of TSV size on multilayer TSV power consumption and delay performance, thereby building the hierarchical reduction TSV structure step by step. Moreover, the influences of TSV height and thickness of oxide layer are discussed. Results show that the model can significantly improve the dynamic power consumption at the expense of little delay. The power consumption optimization reduction is up to 19.52% with 5% delay penalty.