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一种FPGA芯片在射频干扰下的失效机理
引用本文:刘健,陈弟虎,粟涛.一种FPGA芯片在射频干扰下的失效机理[J].强激光与粒子束,2019,31(9):093201-1-093201-6.
作者姓名:刘健  陈弟虎  粟涛
作者单位:中山大学 电子与信息工程学院, 广州 510006
基金项目:国家自然科学基金资助项目61471402广东省科技项目2016B010123005广东省科技项目2015B090912001广东省科技项目2017B0909005
摘    要:研究了一种Xilinx公司FPGA芯片XC7A200T-2FBG676在射频干扰下的失效机理。通过对该FPGA内核供电引脚注入射频干扰发现,某些频率下,随着干扰强度的增大,FPGA会依次出现三种不同类型的失效,分别为该FPGA的内核失效、I/O失效和配置失效。测试分析和HSPICE仿真表明,内核失效是由于BRAM的逻辑层抗扰性差所致,I/O失效是由于射频干扰下输入/输出信号的同时失真所致,配置失效则是由于配置系统读取错误的配置使能信号所致。研究可为该FPGA芯片或者系统电磁兼容设计以及该FPGA抗扰性检测方案的制定提供指导。

关 键 词:FPGA    射频干扰    FPGA内核    FPGA失效
收稿时间:2019-05-13

Failure mechanism of a kind of FPGA chip under RF interference
Institution:School of Electronics and Information Technology, Sun Yat-Sen University, Guangzhou 510006, China
Abstract:The failure mechanism of Xilinx's FPGA chip XC7A200T-2FBG676 under RF interference is studied. When RF interference injects into the power supply pins of the FPGA core, it is found that with the increase of interference intensity at the some frequencies, three types of FPGA failures occur successively, namely core failure, I/O failure and configuration failure. Test analysis and HSPICE simulation show that the core failure is due to the poor disturbance immunity of the logic layer of BRAM, the I/O failure is due to the simultaneous distortion of input/output signals under RF interference, and the configuration failure is due to the configuration system reading the wrong configuration enable signal. This study could provide guidance for the electromagnetic compatibility design of this kind of FPGA chip or system, as well as the formulation of electromagnetic immunity detection scheme of this kind of FPGA.
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