SOI部分耗尽SiGe HBT集电结空间电荷区模型

SOI上的薄膜异质SiGe晶体管通过采用"折叠"集电极,已成功实现SOI上CMOS与HBT的兼容.本文结合SOI薄膜上的纵向SiGe HBT结构模型,提出了包含纵向、横向欧姆电阻和耗尽电容的"部分耗尽 (partially depleted) 晶体管"集电区简化电路模型.基于器件物理及实际考虑,系统建立了外延集电层电场、电势、耗尽宽度模型,并根据该模型对不同器件结构参数进行分析.结果表明,空间电荷区表现为本征集电结耗尽与MOS电容耗尽,空间电荷区宽度随集电结掺杂浓度减小而增大,随集电结反偏电压提高而增大, 关键词： SOI SiGe HBT 集电区 空间电荷区模型     

环栅肖特基势垒金属氧化物半导体场效应管漏致势垒降低效应研究

结合环栅肖特基势垒金属氧化物半导体场效应管(MOSFET)结构, 通过求解圆柱坐标系下的二维泊松方程得到了表面势分布, 并据此建立了适用于低漏电压下的环栅肖特基势垒NMOSFET阈值电压模型.根据计算结果, 分析了漏电压、沟道半径和沟道长度对阈值电压和漏致势垒降低的影响, 对环栅肖特基势垒MOSFET器件以及电路设计具有一定的参考价值. 关键词： 环栅肖特基势垒金属氧化物半导体场效应管 二维泊松方程 阈值电压模型 漏致势垒降低     

Analytical base–collector depletion capacitance in vertical SiGe heterojunction bipolar transistors fabricated on CMOS-compatible silicon on insulator

The base--collector depletion capacitance for vertical SiGe npn heterojunction bipolar transistors (HBTs) on silicon on insulator (SOI) is split into vertical and lateral parts. This paper proposes a novel analytical depletion capacitance model of this structure for the first time. A large discrepancy is predicted when the present model is compared with the conventional depletion model, and it is shown that the capacitance decreases with the increase of the reverse collector--base bias--and shows a kink as the reverse collector--base bias reaches the effective vertical punch-through voltage while the voltage differs with the collector doping concentrations, which is consistent with measurement results. The model can be employed for a fast evaluation of the depletion capacitance of an SOI SiGe HBT and has useful applications on the design and simulation of high performance SiGe circuits and devices.