Collector optimization for tradeoff between breakdown voltage and cut-off frequency in SiGe HBT

As is well known, there exists a tradeoff between the breakdown voltage BVCEOand the cut-off frequency fTfor a standard heterojunction bipolar transistor(HBT). In this paper, this tradeoff is alleviated by collector doping engineering in the SiGe HBT by utilizing a novel composite of P+and N-doping layers inside the collector–base(CB) space-charge region(SCR). Compared with the single N-type collector, the introduction of the thin P+layers provides a reverse electric field weakening the electric field near the CB metallurgical junction without changing the field direction, and the thin Nlayer further effectively lowers the electric field near the CB metallurgical junction. As a result, the electron temperature near the CB metallurgical junction is lowered, consequently suppressing the impact ionization, thus BVCEOis improved with a slight degradation in fT. The results show that the product of fT×BVCEOis improved from 309.51 GHz·V to326.35 GHz·V.     

Effect of lateral structure parameters of SiGe HBTs on synthesized active inductors

The effect of lateral structure parameters of transistors including emitter width, emitter length, and emitter stripe number on the performance parameters of the active inductor(AI), such as the effective inductance Ls, quality factor Q,and self-resonant frequency ω_0 is analyzed based on 0.35-μm Si Ge Bi CMOS process. The simulation results show that for AI operated under fixed current density JC, the HBT lateral structure parameters have significant effect on Ls but little influence on Q and ω_0, and the larger Ls can be realized by the narrow, short emitter stripe and few emitter stripes of Si Ge HBTs. On the other hand, for AI with fixed HBT size, smaller JCis beneficial for AI to obtain larger Ls, but with a cost of smaller Q and ω_0. In addition, under the fixed collector current IC, the larger the size of HBT is, the larger Ls becomes, but the smaller Q and ω_0 become. The obtained results provide a reference for selecting geometry of transistors and operational condition in the design of active inductors.     

A technique for simultaneously improving the product of cutoff frequency–breakdown voltage and thermal stability of SOI SiGe HBT

The product of the cutoff frequency and breakdown voltage( fT×BVCEO) is an important figure of merit(FOM) to characterize overall performance of heterojunction bipolar transistor(HBT). In this paper, an approach to introducing a thin N+-buried layer into N collector region in silicon-on-insulator(SOI) Si Ge HBT to simultaneously improve the FOM of fT×BVCEOand thermal stability is presented by using two-dimensional(2D) numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOI structure, the effects of SOI insulation layer thickness(TBOX) on fT, BVCEO, and the FOM of fT×BVCEOare presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces fT, slightly increases BVCEOto some extent, but ultimately degrades the FOM of fT×BVCEO. Although the fT,BVCEO, and the FOM of fT×BVCEOcan be improved by increasing SOI insulator Si O_2 layer thickness TBOXin SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of Si O_2 layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick TBOX, a thin N+-buried layer is introduced into collector region to not only improve the FOM of fT×BVCEO, but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N+-buried layer in collector region is investigated in detail. The result show that the FOM of fT×BVCEOis improved and the device temperature decreases as the N+-buried layer shifts toward SOI substrate insulation layer. The approach to introducing a thin N+-buried layer into collector region provides an effective method to improve SOI Si Ge HBT overall performance.