A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

A low specific on-resistance(Ron,sp) integrable silicon-on-insulator(SOI) metal-oxide semiconductor field-effect transistor(MOSFET) is proposed and investigated by simulation.The MOSFET features a recessed drain as well as dual gates,which consist of a planar gate and a trench gate extended to the buried oxide layer(BOX)(DGRD MOSFET).First,the dual gates form dual conduction channels,and the extended trench gate also acts as a field plate to improve the electric field distribution.Second,the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path.Third,the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions.All of these sharply reduce Ron,sp and maintain a high breakdown voltage(BV).The BV of 233 V and Ron,sp of 4.151 mΩ·cm2(VGS = 15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch.Compared with the trench gate SOI MOSFET and the conventional MOSFET,Ron,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV,respectively.The trench gate extended to the BOX synchronously acts as a dielectric isolation trench,simplifying the fabrication processes.     

A low specific on-resistance SOI LDMOS with a novel junction field plate

A low specific on-resistance SO1 LDMOS with a novel junction field plate （JFP） is proposed and investigated theo- retically. The most significant feature of the JFP LDMOS is a PP-N junction field plate instead of a metal field plate. The unique structure not only yields charge compensation between the JFP and the drift region, but also modulates the surface electric field. In addition, a trench gate extends to the buffed oxide layer （BOX） and thus widens the vertical conduction area. As a result, the breakdown voltage （BV） is improved and the specific on-resistance （Ron,sp） is decreased significantly. It is demonstrated that the BV of 306 V and the Ron,sp of 7.43 mΩ.cm2 are obtained for the JFP LDMOS. Compared with those of the conventional LDMOS with the same dimensional parameters, the BV is improved by 34.8%, and the Ron,sp is decreased by 56.6% simultaneously. The proposed JFP LDMOS exhibits significant superiority in terms of the trade-off between BV and Ron,sp. The novel JFP technique offers an alternative technique to achieve high blocking voltage and large current capacity for power devices.     

一种N沟VDMOS电离辐射界面陷阱电流传导性研究

利用X射线对一种N沟VDMOS在不同的负载功率下进行了辐射试验,采用电流-电压(I-V)测试方法发现这种H₂-O₂(氢氧合成)氧化栅介质VDMOS样品存在自退火效应时,新增界面陷阱特性与通常的理论不能够很好地一致.根据所测数据,明确提出了有自退火效应样品的新增界面陷阱除了电荷效应外还具有传导电流能力的观点,初步认为该电流是表面费米能级和陷阱能级相互作用导致的产生复合电流,该电流不能简单地从I-V曲线上定量分 关键词： 界面陷阱 亚阈值电流 X射线辐射 VDMOS     

A low specific on-resistance SOI MOSFET with dual gates and recessed drain

A low specific on-resistance (R_on,sp) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce R_on,sp and maintain a high breakdown voltage (BV). The BV of 233 V and R_on,sp of 4.151 mΩ·cm² (V_GS=15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, R_on,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes.