含有本征SiGe层的SiGe异质结双极晶体管集电结耗尽层宽度模型

本文分别建立了含有本征SiGe层的SiGe HBT(异质结双极晶体管)集电结耗尽层各区域的电势、电场分布模型,并在此基础上,建立了集电结耗尽层宽度和延迟时间模型,对该模型进行了模拟仿真,定量地分析了SiGe HBT物理、电学参数对集电结耗尽层宽度和延迟时间的影响,随着基区掺杂浓度和集电结反偏电压的提高,集电结耗尽层延迟时间也随之增大,而随着集电区掺杂浓度的提高和基区Ge组分增加,集电结耗尽层延迟时间随之减小. 关键词： SiGe HBT 集电结耗尽层 延迟时间     

漏致势垒降低效应对短沟道应变硅金属氧化物半导体场效应管阈值电压的影响

结合应变硅金属氧化物半导体场效应管(MOSFET)结构,通过求解二维泊松方程,得到了应变Si沟道的电势分布,并据此建立了短沟道应变硅NMOSFET的阈值电压模型.依据计算结果,详细分析了弛豫Si_1－βGe_β中锗组分β、沟道长度、漏电压、衬底掺杂浓度以及沟道掺杂浓度对阈值电压的影响,从而得到漏致势垒降低效应对小尺寸应变硅器件阈值电压的影响,对应变硅器件以及电路的设计具有重要的参考价值. 关键词： 应变硅金属氧化物半导体场效应管 漏致势垒降低 二维泊松方程 阈值电压模型     

小尺寸应变Si nMOSFET物理模型的研究

本文运用高斯定律得出多晶SiGe栅应变Si nMOSFET的准二维阈值电压模型,并从电流密度方程出发建立了小尺寸应变Si nMOS器件的I-V特性模型.对所得模型进行计算分析,得出沟道Ge组分、多晶Si_1-yGe_y栅Ge组分、栅氧化层厚度、应变Si层厚度、栅长以及掺杂浓度对阈值电压的影响.运用二维器件模拟器对器件表面势和I-V特性进行了仿真,所得结果与模型仿真结果一致,从而证明了模型的正确性. 关键词： 多晶SiGe栅 高斯定理 阈值电压 速度过冲     

多晶SiGe栅量子阱pMOSFET阈值电压模型

本文基于多晶SiGe栅量子阱SiGe pMOSFET器件物理,考虑沟道反型时自由载流子对器件纵向电势的影响,通过求解泊松方程,建立了p+多晶SiGe栅量子阱沟道pMOS阈值电压和表面寄生沟道开启电压模型.应用MATLAB对该器件模型进行了数值分析,讨论了多晶Si_1-yGe_y栅Ge组分、Si_1-xGe_x量子阱沟道Ge组分、栅氧化层厚度、Si帽层厚度、沟道区掺杂浓度和 关键词： 多晶SiGe栅 寄生沟道 量子阱沟道 阈值电压     

Weak avalanche multiplication in SiGe heterojunction bipolar transistors on thin film silicon-on-insulator

In this paper, we propose an analytical avalanche multiplication model for the next generation of SiGe silicon-on-insulator (SOI) heterojunction bipolar transistors (HBTs) and consider their vertical and lateral impact ionizations for the first time. Supported by experimental data, the analytical model predicts that the avalanche multiplication governed by impact ionization shows kinks and the impact ionization effect is small compared with that of the bulk HBT, resulting in a larger base-collector breakdown voltage. The model presented in the paper is significant and has useful applications in the design and simulation of the next generation of SiGe SOI BiCMOS technology.     

Substrate bias effects on collector resistance in SiGe heterojunction bipolar transistors on thin film silicon-on-insulator

An analytical expression for the collector resistance of a novel vertical SiGe heterojunction bipolar transistor(HBT) on thin film silicon-on-insulator(SOI) is obtained with the substrate bias effects being considered.The resistance is found to decrease slowly and then quickly and to have kinks with the increase of the substrate-collector bias,which is quite different from that of a conventional bulk HBT.The model is consistent with the simulation result and the reported data and is useful to the frequency characteristic design of 0.13 μm millimeter-wave SiGe SOI BiCMOS devices.