Mechanical,elastic, anisotropy,and electronic properties of monoclinic phase of m-Si_xGe_(3-x)N_4

The structural,mechanical,elastic anisotropic,and electronic properties of the monoclinic phase of m-Si_3N_4,mSi_2GeN_4,m-SiGe_2N_4,and m-Ge_3N_4are systematically investigated in this work.The calculated results of lattice parameters,elastic constants and elastic moduli of m-Si_3N_4and m-Ge_3N_4are in good agreement with previous theoretical results.Using the Voigt–Reuss–Hill method,elastic properties such as bulk modulus B and shear modulus G are investigated.The calculated ratio of B/G and Poisson’s ratio v show that only m-SiGe_2N_4should belong to a ductile material in nature.In addition,m-SiGe_2N_4possesses the largest anisotropic shear modulus,Young’s modulus,Poisson’s ratio,and percentage of elastic anisotropies for bulk modulus ABand shear modulus AG,and universal anisotropic index AUamong m-Si_xGe_(3-x)N_4(x=0,1,2,3.)The results of electronic band gap reveal that m-Si_3N_4,m-Si_2GeN_4,m-SiGe_2N_4,and m-Ge_3N_4 are all direct and wide band gap semiconducting materials.     

基极注入强电磁脉冲对双极晶体管的损伤效应和机理

建立了双极晶体管(BJT)在强电磁脉冲作用下的二维电热模型, 对处于有源放大区的BJT在基极注入强电磁脉冲时的瞬态响应进行了仿真. 结果表明, BJT烧毁点位置随注入脉冲幅度变化而变化, 低脉冲幅度下晶体管烧毁是由发射结反向雪崩击穿所致, 烧毁点位于发射结柱面区; 而在高脉冲幅度下, 由基区-外延层-衬底组成的p-n-n⁺ 二极管发生二次击穿导致靠近发射极一侧的基极边缘率先烧毁; BJT的烧毁时间随脉冲幅度升高而减小, 而损伤能量则随之呈现减小-增大-减小的变化趋势, 因而存在一个极小值和一个极大值. 仿真与实验结果的比较表明, 本文建立的晶体管模型不但能预测强电磁脉冲作用下BJT内部烧毁发生的位置, 而且能够得到损伤能量. 关键词： 双极晶体管 强电磁脉冲 烧毁点位置 损伤能量     

不同样式的高功率微波对双极晶体管的损伤效应和机理

结合Si基n⁺-p-n-n⁺ 外延平面双极晶体管, 通过分析器件内部的温度分布变化以及电流密度和烧毁时间随信号幅值的变化关系, 研究了其在三角波信号、正弦波信号和方波脉冲信号等三种样式的高功率微波信号作用下的损伤效应和机理. 研究表明, 三种高功率微波信号注入下器件的损伤部位都是发射结, 在频率和信号幅值相同的情况下方波脉冲信号更容易使器件损伤; 位移电流密度和烧毁时间随信号幅值的增大而增大, 而位移电流在总电流所占的比例随信号幅值的增大而减小; 相比于因信号变化率而引起的位移电流, 信号注入功率在高幅值信号注入损伤过程中占主要作用. 利用数据分析软件, 分别得到了三种信号作用下器件烧毁时间和信号频率的变化关系式. 结果表明, 器件烧毁时间随信号频率的增加而增加, 烧毁时间和频率都符合t= af^b的关系式. 关键词： 双极晶体管 高功率微波 损伤机理 信号样式     

Modeling and understanding of the thermal failure induced by high power microwave in CMOS inverter

The thermal failure induced by high power microwave(HPM) in a complementary metal oxide semiconductor(CMOS) inverter is investigated and its dependence on microwave parameters is discussed in detail. An analytical model of the temperature distribution is established and the relationships between hotspot temperature and pulse width and between hotspot temperature and frequency are predicted, which reveals a more severe rise in temperature under the influence of microwave with longer width and lower frequency. The temperature variation mechanism and the theoretical temperature model are validated and explained by the simulation. Furthermore, variation trend of damage threshold with microwave parameters is derived theoretically, and the conclusions are consistent with simulation results and reported data.     

Physics-based analysis and simulation model of electromagnetic interference induced soft logic upset in CMOS inverter

The instantaneous reversible soft logic upset induced by the electromagnetic interference(EMI) severely affects the performances and reliabilities of complementary metal–oxide–semiconductor(CMOS) inverters. This kind of soft logic upset is investigated in theory and simulation. Physics-based analysis is performed, and the result shows that the upset is caused by the non-equilibrium carrier accumulation in channels, which can ultimately lead to an abnormal turn-on of specific metal–oxide–semiconductor field-effect transistor(MOSFET) in CMOS inverter. Then a soft logic upset simulation model is introduced. Using this model, analysis of upset characteristic reveals an increasing susceptibility under higher injection powers, which accords well with experimental results, and the influences of EMI frequency and device size are studied respectively using the same model. The research indicates that in a range from L waveband to C waveband, lower interference frequency and smaller device size are more likely to be affected by the soft logic upset.     

Investigation on latch-up susceptibility induced by high-power microwave in complementary metal–oxide–semiconductor inverter

The latch-up effect induced by high-power microwave(HPM) in complementary metal–oxide–semiconductor(CMOS) inverter is investigated in simulation and theory in this paper. The physical mechanisms of excess carrier injection and HPM-induced latch-up are proposed. Analysis on upset characteristic under pulsed wave reveals increasing susceptibility under shorter-width pulsed wave which satisfies experimental data, and the dependence of upset threshold on pulse repetitive frequency(PRF) is believed to be due to the accumulation of excess carriers. Moreover, the trend that HPMinduced latch-up is more likely to happen in shallow-well device is proposed.Finally, the process of self-recovery which is ever-reported in experiment with its correlation with supply voltage and power level is elaborated, and the conclusions are consistent with reported experimental results.     

Analysis of the damage threshold of the GaAs pseudomorphic high electron mobility transistor induced by the electromagnetic pulse

An electromagnetic pulse(EMP)-induced damage model based on the internal damage mechanism of the Ga As pseudomorphic high electron mobility transistor(PHEMT) is established in this paper. With this model, the relationships among the damage power, damage energy, pulse width and signal amplitude are investigated. Simulation results show that the pulse width index from the damage power formula obtained here is higher than that from the empirical formula due to the hotspot transferring in the damage process of the device. It is observed that the damage energy is not a constant, which decreases with the signal amplitude increasing, and then changes little when the signal amplitude reaches up to a certain level.