XPS, electric and photoluminescence-based analysis of the GaAs (1 0 0) nitridation

In this paper, nitridation process of GaAs (1 0 0) substrates was studied in-situ using X-ray photoelectron spectroscopy (XPS) and ex-situ by means of electrical method I-V and photoluminescence surface state spectroscopy (PLS³) in order to determine chemical, electrical and electronic properties of the elaborated GaN/GaAs interfaces.The elaborated structures were characterised by I-V analysis. The saturation current I_S, the ideality factor n, the barrier height Φ_Bn and the serial resistance R_S are determined.The elaborated GaN/GaAs structures are also exhibited a high PL intensity at room temperature. From the computer-aided analysis of the power-dependent PL efficiency measurements (PLS³ technique), the value of the interface state density N_SS(E) close to the mid-gap was estimated to be in the range of 2-4 × 10¹¹ eV⁻¹ cm⁻², indicating a good electronic quality of the obtained interfaces.Correlation among chemical, electronic and electrical properties of the GaN/GaAs interface was discussed.     

Investigation of diode parameters using I-V and C-V characteristics of In/SiO2/p-Si (MIS) Schottky diodes

A study on interface states density distribution and characteristic parameters of the In/SiO₂/p-Si (MIS) capacitor has been made. The thickness of the SiO₂ film obtained from the measurement of the corrected capacitance in the strong accumulation region for MIS Schottky diodes was 220 Å. The diode parameters from the forward bias I-V characteristics such as ideality factor, series resistance and barrier heights were found to be 1.75, 106-112 Ω and 0.592 eV, respectively. The energy distribution of the interface state density D_it was determined from the forward bias I-V characteristics by taking into account the bias dependence of the effective barrier height. The interface state density obtained using the I-V characteristics had an exponential growth, with bias towards the top of the valance band, from 9.44×10¹³ eV⁻¹ cm⁻² in 0.329-E_v eV to 1.11×10¹³ eV⁻¹ cm⁻² in 0.527-E_v eV at room temperature. Furthermore, the values of interface state density D_it obtained by the Hill-Coleman method from the C-V characteristics range from 52.9×10¹³ to 1.11×10¹³ eV⁻¹ cm⁻² at a frequency range of 30kHz-1 MHz. These values of D_it and R_s were responsible for the non-ideal behaviour of I-V and C-V characteristics.     

Current-voltage characteristics of Au/GaN/GaAs structure

Au/GaN/n-GaAs structure has been fabricated by the electrochemically anodic nitridation method for providing an evidence of achievement of stable electronic passivation of n-doped GaAs surface. The change of the electronic properties of the GaAs surface induced by the nitridation process has been studied by means of current-voltage (I-V) characterizations on Schottky barrier diodes (SBDs) shaped on gallium nitride/gallium arsenide structure. Au/GaN/n-GaAs Schottky diode that showed rectifying behavior with an ideality factor value of 2.06 and barrier height value of 0.73 eV obeys a metal-interfacial layer-semiconductor (MIS) configuration rather than an ideal Schottky diode due to the existence of GaN at the Au/GaAs interfacial layer. The formation of the GaN interfacial layer for the stable passivation of gallium arsenide surface is investigated through calculation of the interface state density N_ss with and without taking into account the series resistance R_s. While the interface state density calculated without taking into account R_s has increased exponentially with bias from 2.2×10¹² cm⁻² eV⁻¹ in (E_c−0.48) eV to 3.85×10¹² cm⁻² eV⁻¹ in (E_c−0.32) eV of n-GaAs, the N_ss obtained taking into account the series resistance has remained constant with a value of 2.2×10¹² cm⁻² eV⁻¹ in the same interval. This has been attributed to the passivation of the n-doped GaAs surface with the formation of the GaN interfacial layer.     

Interface characterization and current conduction in HfO2-gated MOS capacitors

Metal-oxide-semiconductor (MOS) capacitors incorporating hafnium dioxide (HfO₂) dielectrics were fabricated and investigated. In this work, the electrical and interfacial properties were characterized based on capacitance-voltage (C-V) and current-voltage (I-V) measurements. Thereafter the current conduction mechanism, electron effective mass (m*), mean density of interface traps per unit area and energy (), energy distribution of interface traps density and near-interface oxide traps density (N_NIOT) were studied in details. The characterization reveals that the dominant conduction mechanism in the region of high temperature and high field is Schottky emission. The mean density of interface traps per unit area and energy is about 6.3 × 10¹² cm⁻² eV⁻¹ by using high-low frequency capacitance method. The maximum D_it is about 7.76 × 10¹² cm⁻² eV⁻¹ located at 0.27 eV above the valence band.     

Low-temperature oxidation of SiGe by liquid-phase deposition

Low-temperature silicon dioxide (SiO₂) films were grown on silicon germanium (SiGe) surfaces using the liquid-phase deposition (LPD) method. The growth solutions of LPD-SiO₂ are hydrofluorosilicic acid (H₂SiF₆) and boric acid (H₃BO₃). It was found that the growth rate increases with increasing temperature and concentration of H₃BO₃. The Auger electron spectroscopy profile shows that no pileup of Ge atoms occurs at the interface of SiO₂/SiGe after the LPD-SiO₂ growth. Al/LPD-SiO₂/p-SiGe MOS capacitors were prepared to determine capacitance-voltage (C-V) and current-voltage (I-V) characteristics. In our experiments, a low leakage current density of 8.69 × 10⁻⁹ A/cm² under a 2 MV/cm electric field was observed. Such a value is much smaller than those of plasma- and thermal-oxides as a result of no plasma damage and a lower growth temperature. Moreover, lower oxide charges and interface charge densities of 3.82 × 10¹⁰ cm⁻² and 1.12 × 10¹¹ eV⁻¹ cm⁻², respectively, were achieved in our LPD-SiO₂ compared to direct photochemical-vapor-deposition-SiO₂.     

Interface control of high-k gate dielectrics on Ge

Important progress has been made in the passivation of Ge/gate dielectric interfaces. One important approach is by thermally oxidized GeO₂ interface and ALD high-k layers, with an interface state density D_it ∼ 2 × 10¹¹ cm⁻² eV⁻¹. Another approach is with an epi-Si/SiO₂ interface, resulting in similar D_it. Hysteresis and V_th shift, however, are still not optimal. Extensive material characterization and theoretical insights help us understanding the root cause of these remaining issues and show the way to improved interface control.     

The effect of interface states, excess capacitance and series resistance in the Al/SiO2/p-Si Schottky diodes

The current-voltage (I-V) characteristics of Al/SiO₂/p-Si metal-insulator-semiconductor (MIS) Schottky diodes were measured at room temperature. In addition the capacitance-voltage (C-V) and conductance-voltage (G-V) measurements are studied at frequency range of 10 kHz-1 MHz. The higher value of ideality factor of 3.25 was attributed to the presence of an interfacial insulator layer between metal and semiconductor and the high density of interface states localized at Si/SiO₂ interface. The density of interface states (N_ss) distribution profile as a function of (E_ss − E_v) was extracted from the forward bias I-V measurements by taking into account the bias dependence of the effective barrier height (Φ_e) at room temperature for the Schottky diode on the order of ≅4 × 10¹³ eV⁻¹ cm⁻²_. These high values of N_ss were responsible for the non-ideal behaviour of I-V and C-V characteristics. Frequency dispersion in C-V and G-V can be interpreted only in terms of interface states. The N_ss can follow the ac signal especially at low frequencies and yield an excess capacitance. Experimental results show that the I-V, C-V and G-V characteristics of SD are affected not only in N_ss but also in series resistance (R_s), and the location of N_ss and R_s has a significant on electrical characteristics of Schottky diodes.     

Characterization of Y2O3 gate dielectric on n-GaAs substrates

Physical and electrical properties of sputtered deposited Y₂O₃ films on NH₄OH treated n-GaAs substrate are investigated. The as-deposited films and interfacial layer formation have been analyzed by using X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS). It is found that directly deposited Y₂O₃ on n-GaAs exhibits excellent electrical properties with low frequency dispersion (<5%), hysteresis voltage (0.24 V), and interface trap density (3 × 10¹² eV⁻¹ cm⁻²). The results show that the deposition of Y₂O₃ on n-GaAs can be an effective way to improve the interface quality by the suppression on native oxides formation, especially arsenic oxide which causes Fermi level pinning at high-k/GaAs interface. The Al/Y₂O₃/n-GaAs stack with an equivalent oxide thickness (EOT) of 2.1 nm shows a leakage current density of 3.6 × 10⁻⁶ A cm⁻² at a V_FB of 1 V. While the low-field leakage current conduction mechanism has been found to be dominated by the Schottky emission, Poole-Frenkel emission takes over at high electric fields. The energy band alignment of Y₂O₃ films on n-GaAs substrate is extracted from detailed XPS measurements. The valence and conduction band offsets at Y₂O₃/n-GaAs interfaces are found to be 2.14 and 2.21 eV, respectively.     

Improved electrical and interfacial properties of RF-sputtered HfAlOx on n-GaAs with effective Si passivation

In this paper, we present the effects of ultrathin Si interfacial layer on the physical and electrical properties of GaAs MOS capacitors fabricated using RF-sputtered HfAlO_x gate dielectric. It is found that HfAlO_x/Si/n-GaAs stack exhibits excellent electrical properties with low frequency dispersion (∼4.8%), hysteresis voltage (0.27 V) and interface trap density (1.3 × 10¹² eV⁻¹ cm⁻²). The current density of 3.7 × 10⁻⁵ A/cm² is achieved with an equivalent-oxide-thickness of 1.8 nm at V_FB + 1 V for Si-passivated HfAlO_x films on n-GaAs. X-ray photoelectron spectroscopy (XPS) analysis shows that the suppression of low-k interfacial layer formation is accomplished with the introduction of ultrathin Si interface control layer (ICL). Thus the introduction of thin layer of Si between HfAlO_x dielectrics and GaAs substrate is an effective way to improve the interface quality such as low frequency dispersion, hysteresis voltage and leakage current. Additionally, current conduction mechanism has been studied and the dominant conduction mechanisms are found to be Schottky emission at low to medium electric fields and Poole-Frenkel at high fields and high temperatures under substrate injection. In case of gate injection, the main current conduction at low field is found to be the Schottky emission at high temperatures.     

Illumination dependence of I-V and C-V characterization of Au/InSb/InP(1 0 0) Schottky structure

The effects of surface preparation and illumination on electric parameters of Au/InSb/InP(100) Schottky diode were investigated, in the later diode InSb forms a fine restructuration layer allowing to block In atoms migration to surface. In order to study the electric characteristics under illumination, we make use of an He-Ne laser of 1 mW power and 632.8 nm wavelength. The current-voltage I(V_G), the capacitance-voltage C(V_G) measurements were plotted and analysed. The saturation current I_s, the serial resistance R_s and the mean ideality factor n are, respectively, equal to 2.03 × 10⁻⁵ A, 85 Ω, 1.7 under dark and to 3.97 × 10⁻⁵ A, 67 Ω, 1.59 under illumination. The analysis of I(V_G) and C(V_G) characteristics allows us to determine the mean interfacial state density N_ss and the transmission coefficient θ_n equal, respectively, to 4.33 × 10¹² eV⁻¹ cm⁻², 4.08 × 10⁻³ under dark and 3.79 × 10¹² eV⁻¹ cm⁻² and 5.65 × 10⁻³ under illumination. The deep discrete donor levels presence in the semiconductor bulk under dark and under illumination are responsible for the non-linearity of the C⁻²(V_G) characteristic.     

Study of HfSiO film prepared by electron beam evaporation for high-k gate dielectric applications

The purpose of this paper is to report some experimental results with HfSiO films formed on silicon substrates by electron beam evaporation (EB-PVD) and annealed at different temperatures. The images of atomic force microscope (AFM) indicated that HfSiO film annealed at 900 °C was still amorphous, with a surface roughness of 0.173 nm. X-ray photoelectron spectroscopy (XPS) analysis revealed that the chemical composition of the film was (HfO₂)₃(SiO₂) and Hf-Si-O bonds existed in the annealed film. Electrical measurements showed that the equivalent oxide thickness (EOT) was 4 nm, the dielectric constant was around 6, the breakdown voltage was 10 MV/cm, the fixed charge density was −1.2 × 10¹² cm⁻², and the leakage current was 0.4 μA/cm² at the gate bias of 2 V for 6 nm HfSiO film. The annealing after deposition effectively reduced trapping density and the leakage current, and eliminated hysteresis in the C-V curves. Annealing also induced SiO₂ growth at the interface.     

The conductance and capacitance-frequency characteristics of Au/pyronine-B/p-type Si/Al contacts

The rectifying junction characteristics of the organic compound pyronine-B (PYR-B) film on a p-type Si substrate have been studied. The PYR-B has been evaporated onto the top of p-Si surface. The barrier height and ideality factor values of 0.67 ± 0.02 eV and 2.02 ± 0.03 for this structure have been obtained from the forward bias current-voltage (I-V) characteristics. The energy distribution of the interface states and their relaxation time have been determined from the forward bias capacitance-frequency and conductance-frequency characteristics in the energy range of ((0.42 ± 0.02) − E_v)-((0.66 ± 0.02) − E_v) eV. The interface state density values ranges from (4.21 ± 0.14) × 10¹³ to (3.82 ± 0.24) × 10¹³ cm⁻² eV⁻¹. Furthermore, the relaxation time ranges from (1.65 ± 0.23) × 10⁻⁵ to (8.12 ± 0.21) × 10⁻⁴ s and shows an exponential rise with bias from the top of the valance band towards the midgap.     

Some electrical and structural properties of Cd/CdS/n–Si/Au–Sb sandwich structure

In view of CdS growth is very impotent for technological importance especially solar applications; synthesis of this material remains a topic of great interest for researchers by means of an economically and technically viable method. In the present paper, Cd/CdS/n–Si/Au–Sb sandwich structure has been grown by Successive Ionic Layer Adsorption and Reaction (SILAR) technique. For investigating the structural properties, X-ray diffraction (XRD), scanning electron microscopy (SEM) and energy dispersive X-ray analysis (EDAX) measurements have been performed and it has been seen that films exhibit polycrystalline behavior. The capacitance–voltage (C–V) and conductance/w-voltage (G/w–V) characteristics of Cd/CdS/n–Si/Au–Sb structure have been investigated by considering series resistance and interface states effects. These measurements have been done in the −4 V, 4 V voltage range and in the frequency range of 10 kHz–3 MHz at room temperature. It is seen that, the series resistance (R_s) and interface state density have been strongly depend on frequency. The barrier height, donor concentration, diffusion potential parameters have been determined from the linear C⁻²–V plot. The barrier height values are obtained between 0.495 and 0.796 eV and doping density values have been ranged from 1.455 × 10¹⁴ to 1.999 × 10¹⁴ cm⁻³respectively. The capacitance–frequency (C–f) and conductance/w-frequency (G/w–f) characteristics of Cd/CdS/n–Si/Au–Sb structures have been measured at the various biases 0.00–0.14 V at room temperature. The energy distribution of the interface states (N_ss) and their relaxation time (τ) have been determined from the forward bias capacitance–frequency characteristics. The N_ss and τ values have ranged from 2.01 × 10¹² cm⁻² eV⁻¹and 9.68 × 10⁻⁴ s in (Ec-0.45) eV–2.86 × 10¹³ cm⁻² eV⁻¹ and 3.81 × 10⁻⁴ s in (Ec-0.75) eV, respectively.     

Electrical characteristics of insulating aluminum nitride MIS nanostructures

Capacitance-voltage measurements of high quality PECVD and MBE grown aluminum nitride (AlN) thin films have been performed. The prepared films have shown polycrystalline (0 0 2)-preferential orientation, and were deposited on p-type Si (1 0 0) substrates with Pt forming the metal gate in a metal-insulator-semiconductor (MIS) configuration. The structure, crystallinity, texture and insulating properties have been found to depend on film thickness and were substantially influenced by the increase of the thickness. C-V measurements of the epitaxial and PECVD films were carried out and their insulating characteristics with increasing thickness (200-1000 nm) were investigated. The epitaxial films exhibited no hysteresis in capacitance behaviour, owing to better crystalline quality over the PECVD grown ones. Capacitance curves versus bias voltage have also been acquired at different temperatures; 10 K, 30 K and 50 K for deposited polycrystalline AlN films of (0 0 2) orientation. We have found that the defects trapped in the Pt/AlN/Si structure played a key role in dominating the overall behaviour of the C-V measurement curves. The trapped charges at the interface between the AlN insulating film and Si substrate caused the capacitance characteristics to shift to negative voltages, and the estimated charge density was of the order of 10¹⁰ and 10⁸ cm⁻² eV⁻¹ for the PECVD and epitaxial samples respectively. The I-V measurements referred to space-charge conduction mechanism, and the deduced leakage current was found to be of the order of 10⁻⁹ A at 200 nm film thickness.     

Evaluating effect of surface state density at the interfaces in degraded bulk heterojunction organic solar cell

Degradation and short shelf life have been observed experimentally in poly(3-hexylthiophene) (P3HT): 6,6-phenyl C61-butyric acid methyl ester (PCBM) based blend solar cells. Both dark and illuminated current–voltage characteristics could be explained quantitatively with a proposed single model for a typical degraded organic solar cell-glass/ITO/PEDOT:PSS/P3HT:PCBM/Al. It has been found that surface state density, interface thickness, tunneling coefficient and occupation probabilities of the interface states becomes important with the passage of time. To look into the problem the activity at ITO/PEDOT:PSS and P3HT:PCBM/Al interfaces are studied using realistic values of the interfaces. The experimental J–V characteristics is well explained with the inclusion of tunneling current through these surface states and becomes the dominant current component for the degraded cell. It is also found that surface state density increases to 10¹²–10¹³ cm⁻² eV⁻¹, which has been verified with C–V measurements and also is in agreement with our proposed model for BHJ solar cell after 150 h of fabrication.     

High-quality two-dimensional electron gas at large scale GaN/AlGaN wafer interface prepared by mass production MOCVD systems

Basic electronic properties of two-dimensional electron gas (2DEG) formed at GaN/AlGaN hetero-interface in large-scale (100 mm) wafer made by metal organic chemical vapour deposition (MOCVD) have been reported and discussed. From conventional Hall measurements, highest electron mobility was found to be μ_e∼1680 and 9000 cm²/V s at room temperature and at ∼5 K, respectively, for sheet electron density of n_s∼8×10¹² cm⁻². In magneto-resistance (MR) measurements carried out at 1.5 K in Hall bar sample defined by photolithography and ion implantation, very clear Schubnikov de-Haas oscillations and integer quantum Hall effect were observed in diagonal (R_xx) and off-diagonal (R_xy) resistances, respectively. In addition, a good insulating nature of GaN layer is confirmed by capacitance-voltage (C-V) measurement. These results suggest the high-qualitiness of our 100 mm GaN/AlGaN high electron mobility transistor (HEMT) wafers comparable to those so far reported.     

Characterization of cubic phase MgZnO/Si(1 0 0) interfaces

The microstructural properties of the Mg_xZn_1−xO/Si(1 0 0) interface were investigated using transmission electron microscopy (TEM) and chemical states of the heterostructure were studied by high resolution X-ray photoelectron spectroscopy (XPS). By analyzing the valence band spectra of thin Mg_xZn_1−xO/Si(1 0 0) heterostructures, the valence band offset between such Mg_0.55Zn_0.45O and Si(1 0 0) was obtained to be 2.3 eV. Using the cubic ternary thin films as insulators, metal-insulator-semiconductor (MIS) capacitors have been fabricated. Leakage current density lower than 3 × 10⁻⁷ A/cm² is obtained under the electrical field of 600 kV/cm by current-voltage (I-V) measurement. Frenkel-Poole conduction mechanism is the main cause of current leakage under high electrical field.     

DC conductivity of silver vanadium tellurite glasses

The mixed electronic-ionic conduction in 0.5[xAg₂O-(1−x)V₂O₅]-0.5TeO₂ glasses with x=0.1-0.8 has been investigated over a wide temperature range (70-425 K). The mechanism of dc conductivity changes from predominantly electronic to ionic within the 30?mol% Ag₂O?40 range; it is correlated with the underlying change in glass structure. The temperature dependence of electronic conductivity has been analyzed quantitatively to determine the applicability of various models of conduction in amorphous semiconducting glasses. At high temperature, T>θ_D/2 (where θ_D is the Debye temperature) the electronic dc conductivity is due to non-adiabatic small polaron hopping of electrons for 0.1?x?0.5. The density of states at Fermi level is estimated to be N(E_F)≈10¹⁹-10²⁰ eV⁻¹ cm⁻³. The carrier density is of the order of 10¹⁹ cm⁻³, with mobility ≈2.3×10⁻⁷-8.6×10⁻⁹ cm² V⁻¹ s⁻¹ at 300 K. The electronic dc conductivity within the whole range of temperature is best described in terms of Triberis-Friedman percolation model. For 0.6?x?0.8, the predominantly ionic dc conductivity is described well by the Anderson-Stuart model.     

Trap-controlled behavior in ultrathin Lu2O3 high-k gate dielectrics

Amorphous Lu₂O₃ high-k gate dielectrics were grown directly on n-type (100) Si substrates by the pulsed laser deposition (PLD) technique. High-resolution transmission electron microscope (HRTEM) observation illustrated that the Lu₂O₃ film has amorphous structure and the interface with Si substrate is free from amorphous SiO₂. An equivalent oxide thickness (EOT) of 1.1 nm with a leakage current density of 2.6×10⁻⁵ A/cm² at 1 V accumulation bias was obtained for 4.5 nm thick Lu₂O₃ thin film deposited at room temperature followed by post-deposition anneal (PDA) at 600 °C in oxygen ambient. The effects of PDA process and light illumination were studied by capacitance-voltage (C-V) and current density-voltage (J-V) measurements. It was proposed that the net fixed charge density and leakage current density could be altered significantly depending on the post-annealing conditions and the capability of traps to trap and release charges.     

Interface properties of an O2 annealed Au/Ni/n-Al0.18Ga0.82N Schottky contact

We oxidized a Ni/Au metal bi-layer contact fabricated on HVPE Al_0.18Ga_0.82N from 373 K to 573 K in 100 K steps. In the range 1 kHz to 2 MHz, the Capacitance–Voltage–Frequency (C–V–f) measurements reveal a frequency dispersion of the capacitance and the presence of an anomalous peak at 0.4 V owing to the presence of interface states in the as deposited contact system. The dispersion was progressively removed by O₂ anneals from temperatures as low as 373 K. These changes are accompanied by an improvement in the overall quality of the Schottky system: the ideality factor, n, improves from 2.09 to 1.26; the Schottky barrier height (SBH), determined by the Norde [1] method, increases from 0.72 eV to 1.54 eV. From the Nicollian and Goetzberger model [2], we calculated the energy distribution of the density of interface states, N_SS. Around 1 eV above the Al_0.18Ga_0.82N valence band, N_SS, decreases from 2.3×10¹² eV⁻¹ cm⁻² for the un-annealed diodes to 1.3×10¹² eV⁻¹ cm⁻² after the 573 K anneal. Our results suggest the formation of an insulating NiO leading to a MIS structure for the oxidized Au/Ni/Al_0.18Ga_0.82N contact.