Interface control of high-k gate dielectrics on Ge

Important progress has been made in the passivation of Ge/gate dielectric interfaces. One important approach is by thermally oxidized GeO₂ interface and ALD high-k layers, with an interface state density D_it ∼ 2 × 10¹¹ cm⁻² eV⁻¹. Another approach is with an epi-Si/SiO₂ interface, resulting in similar D_it. Hysteresis and V_th shift, however, are still not optimal. Extensive material characterization and theoretical insights help us understanding the root cause of these remaining issues and show the way to improved interface control.     

Interface characterization and current conduction in HfO2-gated MOS capacitors

Metal-oxide-semiconductor (MOS) capacitors incorporating hafnium dioxide (HfO₂) dielectrics were fabricated and investigated. In this work, the electrical and interfacial properties were characterized based on capacitance-voltage (C-V) and current-voltage (I-V) measurements. Thereafter the current conduction mechanism, electron effective mass (m*), mean density of interface traps per unit area and energy (), energy distribution of interface traps density and near-interface oxide traps density (N_NIOT) were studied in details. The characterization reveals that the dominant conduction mechanism in the region of high temperature and high field is Schottky emission. The mean density of interface traps per unit area and energy is about 6.3 × 10¹² cm⁻² eV⁻¹ by using high-low frequency capacitance method. The maximum D_it is about 7.76 × 10¹² cm⁻² eV⁻¹ located at 0.27 eV above the valence band.     

Effect of plasma treatment on interface property of BCN/GaN structure

Interface properties of BCN/GaN metal-insulator-semiconductor (MIS) structures are investigated by X-ray photoelectron spectroscopy (XPS) and capacitance versus voltage (C-V) characteristics measurements. The BCN/GaN samples are fabricated by in situ process consisting of plasma treatment and deposition of BCN film in the plasma-assisted chemical vapor deposition (PACVD) apparatus. XPS measurement shows that the oxide formation at the BCN/GaN interface is suppressed by nitrogen (N₂) and hydrogen (H₂) plasma treatment. The interface state density is estimated from C-V characteristics measured at 1 MHz using Terman method. The minimum interface state density appears from 0.2 to 0.7 eV below the conduction band edge of GaN. The minimum value of the interface state density is estimated to be 3.0 × 10¹⁰ eV⁻¹ cm⁻² for the BCN/GaN structure with mixed N₂ and H₂ plasma treatment for 25 min. Even after annealing at 430 °C for 10 min, the interface state density as low as 6.0 × 10¹⁰ eV⁻¹ cm⁻² is maintained.     

Illumination dependence of I-V and C-V characterization of Au/InSb/InP(1 0 0) Schottky structure

The effects of surface preparation and illumination on electric parameters of Au/InSb/InP(100) Schottky diode were investigated, in the later diode InSb forms a fine restructuration layer allowing to block In atoms migration to surface. In order to study the electric characteristics under illumination, we make use of an He-Ne laser of 1 mW power and 632.8 nm wavelength. The current-voltage I(V_G), the capacitance-voltage C(V_G) measurements were plotted and analysed. The saturation current I_s, the serial resistance R_s and the mean ideality factor n are, respectively, equal to 2.03 × 10⁻⁵ A, 85 Ω, 1.7 under dark and to 3.97 × 10⁻⁵ A, 67 Ω, 1.59 under illumination. The analysis of I(V_G) and C(V_G) characteristics allows us to determine the mean interfacial state density N_ss and the transmission coefficient θ_n equal, respectively, to 4.33 × 10¹² eV⁻¹ cm⁻², 4.08 × 10⁻³ under dark and 3.79 × 10¹² eV⁻¹ cm⁻² and 5.65 × 10⁻³ under illumination. The deep discrete donor levels presence in the semiconductor bulk under dark and under illumination are responsible for the non-linearity of the C⁻²(V_G) characteristic.     

The conductance and capacitance-frequency characteristics of Au/pyronine-B/p-type Si/Al contacts

The rectifying junction characteristics of the organic compound pyronine-B (PYR-B) film on a p-type Si substrate have been studied. The PYR-B has been evaporated onto the top of p-Si surface. The barrier height and ideality factor values of 0.67 ± 0.02 eV and 2.02 ± 0.03 for this structure have been obtained from the forward bias current-voltage (I-V) characteristics. The energy distribution of the interface states and their relaxation time have been determined from the forward bias capacitance-frequency and conductance-frequency characteristics in the energy range of ((0.42 ± 0.02) − E_v)-((0.66 ± 0.02) − E_v) eV. The interface state density values ranges from (4.21 ± 0.14) × 10¹³ to (3.82 ± 0.24) × 10¹³ cm⁻² eV⁻¹. Furthermore, the relaxation time ranges from (1.65 ± 0.23) × 10⁻⁵ to (8.12 ± 0.21) × 10⁻⁴ s and shows an exponential rise with bias from the top of the valance band towards the midgap.     

Current-voltage characteristics of Au/GaN/GaAs structure

Au/GaN/n-GaAs structure has been fabricated by the electrochemically anodic nitridation method for providing an evidence of achievement of stable electronic passivation of n-doped GaAs surface. The change of the electronic properties of the GaAs surface induced by the nitridation process has been studied by means of current-voltage (I-V) characterizations on Schottky barrier diodes (SBDs) shaped on gallium nitride/gallium arsenide structure. Au/GaN/n-GaAs Schottky diode that showed rectifying behavior with an ideality factor value of 2.06 and barrier height value of 0.73 eV obeys a metal-interfacial layer-semiconductor (MIS) configuration rather than an ideal Schottky diode due to the existence of GaN at the Au/GaAs interfacial layer. The formation of the GaN interfacial layer for the stable passivation of gallium arsenide surface is investigated through calculation of the interface state density N_ss with and without taking into account the series resistance R_s. While the interface state density calculated without taking into account R_s has increased exponentially with bias from 2.2×10¹² cm⁻² eV⁻¹ in (E_c−0.48) eV to 3.85×10¹² cm⁻² eV⁻¹ in (E_c−0.32) eV of n-GaAs, the N_ss obtained taking into account the series resistance has remained constant with a value of 2.2×10¹² cm⁻² eV⁻¹ in the same interval. This has been attributed to the passivation of the n-doped GaAs surface with the formation of the GaN interfacial layer.     

Structural, optical properties and VCNR mechanisms in vacuum evaporated iodine doped ZnSe thin films

Iodine doped ZnSe thin films were prepared onto uncoated and aluminium (Al) coated glass substrates using vacuum evaporation technique under a vacuum of 3 × 10⁻⁵ Torr. The composition, structural, optical and electrical properties of the deposited films were analyzed using Rutherford backscattering spectrometry (RBS), X-ray diffraction (XRD), spectroscopic ellipsometry (SE) and study of I-V characteristics, respectively. In the RBS analysis, the composition of the deposited film is calculated as ZnSeI_0.003. The X-ray diffractograms reveals the cubic structure of the film oriented along (1 1 1) direction. The structural parameters such as crystallite size, strain and dislocation density values are calculated as 32.98 nm, 1.193 × 10⁻³ lin⁻² m⁻⁴ and 9.55 × 10¹⁴ lin/m², respectively. Spectroscopic ellipsometric (SE) measurements were also presented for the prepared iodine doped ZnSe thin films. The optical band gap value of the deposited films was calculated as 2.681 eV by using the optical transmittance measurements and the results are discussed. In the electrical studies, the deposited films exhibit the VCNR conduction mechanism. The iodine doped ZnSe films show the non-linear I-V characteristics and switching phenomena.     

The effect of interface states, excess capacitance and series resistance in the Al/SiO2/p-Si Schottky diodes

The current-voltage (I-V) characteristics of Al/SiO₂/p-Si metal-insulator-semiconductor (MIS) Schottky diodes were measured at room temperature. In addition the capacitance-voltage (C-V) and conductance-voltage (G-V) measurements are studied at frequency range of 10 kHz-1 MHz. The higher value of ideality factor of 3.25 was attributed to the presence of an interfacial insulator layer between metal and semiconductor and the high density of interface states localized at Si/SiO₂ interface. The density of interface states (N_ss) distribution profile as a function of (E_ss − E_v) was extracted from the forward bias I-V measurements by taking into account the bias dependence of the effective barrier height (Φ_e) at room temperature for the Schottky diode on the order of ≅4 × 10¹³ eV⁻¹ cm⁻²_. These high values of N_ss were responsible for the non-ideal behaviour of I-V and C-V characteristics. Frequency dispersion in C-V and G-V can be interpreted only in terms of interface states. The N_ss can follow the ac signal especially at low frequencies and yield an excess capacitance. Experimental results show that the I-V, C-V and G-V characteristics of SD are affected not only in N_ss but also in series resistance (R_s), and the location of N_ss and R_s has a significant on electrical characteristics of Schottky diodes.     

On the energy distribution profile of interface states obtained by taking into account of series resistance in Al/TiO2/p-Si (MIS) structures

The energy distribution profile of the interface states (N_ss) of Al/TiO₂/p-Si (MIS) structures prepared using the sol-gel method was obtained from the forward bias current-voltage (I-V) characteristics by taking into account both the bias dependence of the effective barrier height (?_e) and series resistance (R_s) at room temperature. The main electrical parameters of the MIS structure such as ideality factor (n), zero-bias barrier height (?_b0) and average series resistance values were found to be 1.69, 0.519 eV and 659 Ω, respectively. This high value of n was attributed to the presence of an interfacial insulator layer at the Al/p-Si interface and the density of interface states (N_ss) localized at the Si/TiO₂ interface. The values of N_ss localized at the Si/TiO₂ interface were found with and without the R_s at 0.25-E_v in the range between 8.4×10¹³ and 4.9×10¹³ eV⁻¹ cm⁻². In addition, the frequency dependence of capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics of the structures have been investigated by taking into account the effect of N_ss and R_s at room temperature. It can be found out that the measured C and G/ω are strongly dependent on bias voltage and frequency.     

Stabilization of a very high-k crystalline ZrO2 phase by post deposition annealing of atomic layer deposited ZrO2/La2O3 dielectrics on germanium

The impact of the ZrO₂/La₂O₃ film thickness ratio and the post deposition annealing in the temperature range between 400 °C and 600 °C on the electrical properties of ultrathin ZrO₂/La₂O₃ high-k dielectrics grown by atomic layer deposition on (1 0 0) germanium is investigated. As-deposited stacks have a relative dielectric constant of 24 which is increased to a value of 35 after annealing at 500 °C due to the stabilization of tetragonal/cubic ZrO₂ phases. This effect depends on the absolute thickness of ZrO₂ within the dielectric stack and is limited due to possible interfacial reactions at the oxide/Ge interface. We show that adequate processing leads to very high-k dielectrics with EOT values below 1 nm, leakage current densities in the range of 0.01 A/cm², and interface trap densities in the range of 2-5 × 10¹² eV⁻¹ cm⁻².     

Characterization of Y2O3 gate dielectric on n-GaAs substrates

Physical and electrical properties of sputtered deposited Y₂O₃ films on NH₄OH treated n-GaAs substrate are investigated. The as-deposited films and interfacial layer formation have been analyzed by using X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS). It is found that directly deposited Y₂O₃ on n-GaAs exhibits excellent electrical properties with low frequency dispersion (<5%), hysteresis voltage (0.24 V), and interface trap density (3 × 10¹² eV⁻¹ cm⁻²). The results show that the deposition of Y₂O₃ on n-GaAs can be an effective way to improve the interface quality by the suppression on native oxides formation, especially arsenic oxide which causes Fermi level pinning at high-k/GaAs interface. The Al/Y₂O₃/n-GaAs stack with an equivalent oxide thickness (EOT) of 2.1 nm shows a leakage current density of 3.6 × 10⁻⁶ A cm⁻² at a V_FB of 1 V. While the low-field leakage current conduction mechanism has been found to be dominated by the Schottky emission, Poole-Frenkel emission takes over at high electric fields. The energy band alignment of Y₂O₃ films on n-GaAs substrate is extracted from detailed XPS measurements. The valence and conduction band offsets at Y₂O₃/n-GaAs interfaces are found to be 2.14 and 2.21 eV, respectively.     

Effect of UV lamp irradiation during oxidation of Zr/Pt/Si structure on electrical properties of Pt/ZrO2/Pt/Si structure

Metal-insulator-metal (MIM) capacitors were fabricated using ZrO₂ films and the effects of structural and native defects of the ZrO₂ films on the electrical and dielectric properties were investigated. For preparing ZrO₂ films, Zr films were deposited on Pt/Si substrates by ion beam deposition (IBD) system with/without substrate bias voltages and oxidized at 200 °C for 60 min under 0.1 MPa O₂ atmosphere with/without UV light irradiation (λ = 193 nm, Deep UV lamp). The ZrO₂(∼12 nm) films on Pt(∼100 nm)/Si were characterized by X-ray diffraction pattern (XRD), field emission scanning electron microscopy (FE-SEM) and high-resolution transmission electron microscopy (HRTEM), capacitance-voltage (C-V) and current-voltage (I-V) measurements were carried out on MIM structures. ZrO₂ films, fabricated by oxidizing the Zr film deposited with substrate bias voltage under UV light irradiation, show the highest capacitance (784 pF) and the lowest leakage current density. The active oxygen species formed by UV irradiation are considered to play an important role in the reduction of the leakage current density, because they can reduce the density of oxygen vacancies.     

The dependence of barrier height on temperature for Pd Schottky contacts on ZnO

Temperature dependent current-voltage (I-V) and capacitance-voltage (C-V) measurements have been performed on Pd/ZnO Schottky barrier diodes in the range 60-300 K. The room temperature values for the zero bias barrier height from the I-V measurements (Φ_I-V) was found to be 0.52 eV and from the C-V measurements (Φ_C-V) as 3.83 eV. From the temperature dependence of forward bias I-V, the barrier height was observed to increase with temperature, a trend that disagrees with the negative temperature coefficient for semiconductor material. The C-V barrier height decreases with temperature, a trend that is in agreement with the negative temperature coefficient of semiconductor material. This has enabled us to fit two curves in two regions (60-120 K and 140-300 K). We have attributed this behaviour to a defect observed by DLTS with energy level 0.31 eV below the conduction band and defect concentration of between 4×10¹⁶ and 6×10¹⁶ cm⁻³ that traps carriers, influencing the determination of the barrier height.     

C-V analysis of rapidly thermal annealed SF6 plasma treated AlGaN/GaN heterostructures

We studied influence of rapid thermal annealing on electrical parameters of SF₆ plasma treated AlGaN/GaN heterostructures. The main emphasis by the evaluation was laid on C-V measurement and simulation, but also I-V and SIMS measurement were used. It was found that the diminished sheet carrier concentration of a two-dimensional electron gas after plasma treatment recovered significantly at the temperature of 500 °C. By using C-V measurement, it was possible to assess besides the changes of the two-dimensional electron gas concentration after annealing also the changes in the Schottky barrier heights and to find out the doping concentration in AlGaN barrier and GaN channel layer. The trend in Schottky barrier height changes after annealing was confirmed also by I-V measurement.     

High-k Al2O3 MOS structures with Si interface control layer formed on air-exposed GaAs and InGaAs wafers

This paper attempts to realize unpinned high-k insulator-semiconductor interfaces on air-exposed GaAs and In_0.53Ga_0.47As by using the Si interface control layer (Si ICL). Al₂O₃ was deposited by ex situ atomic layer deposition (ALD) as the high-k insulator. By applying an optimal chemical treatment using HF acid combined with subsequent thermal cleaning below 500 °C in UHV, interface bonding configurations similar to those by in situ UHV process were achieved both for GaAs and InGaAs after MBE growth of the Si ICL with no trace of residual native oxide components. As compared with the MIS structures without Si ICL, insertion of Si ICL improved the electrical interface quality, a great deal both for GaAs and InGaAs, reducing frequency dispersion of capacitance, hysteresis effects and interface state density (D_it). A minimum value of D_it of 2 × 10¹¹ eV⁻¹ cm⁻² was achieved both for GaAs and InGaAs. However, the range of bias-induced surface potential excursion within the band gap was different, making formation of electron layer by surface inversion possible in InGaAs, but not possible in GaAs. The difference was explained by the disorder induced gap state (DIGS) model.     

C-V studies on metal-ferroelectric bismuth vanadate (Bi2VO5.5)-semiconductor structure

Ferroelectric bismuth vanadate Bi₂VO_5.5 (BVO) thin films have been successfully grown on p-type Si(100) substrate by using chemical solution decomposition (CSD) technique followed by rapid thermal annealing (RTA). The crystalline nature of the films has been studied by X-ray diffraction (XRD). Atomic force microscopy (AFM) was used to study the microstructure of the films. The dielectric properties of the films were studied. The capacitance-voltage characteristics have been studied in metal-ferroelectric-insulator-semiconductor (MFIS) configuration. The dielectric constant of BVO thin films formed on Si(100) is about 146 measured at a frequency of 100 kHz at room temperature. The capacitance-voltage plot of a Bi₂VO_5.5 MFIS capacitor subjected to a dc polarizing voltages shows a memory window of 1.42 V during a sweep of ±5 V gate bias. The flatband voltage (V_f) shifts towards the positive direction rather than negative direction. This leads to the asymmetric behavior of the C-V curve and decrease in memory window. The oxide trap density at a ramp rate of 0.2 V/s was estimated to be as high as 1.45×10¹² cm⁻².     

Electronic properties of the metal/organic interlayer/inorganic semiconductor sandwich device

In this study, we prepared a Metal(Al)/Organic Interlayer(Congo Red=CR)/Inorganic Semiconductor (p-Si) (MIS) Schottky device formed by coating of an organic film on p-Si semiconductor wafer. The Al/CR/p-Si MIS device had a good rectifying behavior. By using the forward bias I-V characteristics, the values of ideality factor (n) and barrier height (Φ_b) for the Al/CR/p-Si MIS device were obtained as 1.68 and 0.77 eV, respectively. It was seen that the Φ_b value of 0.77 eV calculated for the Al/CR/p-Si MIS device was significantly higher than value of 0.50 eV of the conventional Al/p-Si Schottky diodes. Modification of the interfacial potential barrier of the Al/p-Si diode was achieved by using a thin interlayer of the CR organic material. This was attributed to the fact that the CR organic interlayer increased the effective barrier height by influencing the space charge region of Si. The interface-state density of the MIS diode was found to vary from 1.24×10¹³ to 2.44×10¹² eV⁻¹ cm⁻².     

Some electrical and structural properties of Cd/CdS/n–Si/Au–Sb sandwich structure

In view of CdS growth is very impotent for technological importance especially solar applications; synthesis of this material remains a topic of great interest for researchers by means of an economically and technically viable method. In the present paper, Cd/CdS/n–Si/Au–Sb sandwich structure has been grown by Successive Ionic Layer Adsorption and Reaction (SILAR) technique. For investigating the structural properties, X-ray diffraction (XRD), scanning electron microscopy (SEM) and energy dispersive X-ray analysis (EDAX) measurements have been performed and it has been seen that films exhibit polycrystalline behavior. The capacitance–voltage (C–V) and conductance/w-voltage (G/w–V) characteristics of Cd/CdS/n–Si/Au–Sb structure have been investigated by considering series resistance and interface states effects. These measurements have been done in the −4 V, 4 V voltage range and in the frequency range of 10 kHz–3 MHz at room temperature. It is seen that, the series resistance (R_s) and interface state density have been strongly depend on frequency. The barrier height, donor concentration, diffusion potential parameters have been determined from the linear C⁻²–V plot. The barrier height values are obtained between 0.495 and 0.796 eV and doping density values have been ranged from 1.455 × 10¹⁴ to 1.999 × 10¹⁴ cm⁻³respectively. The capacitance–frequency (C–f) and conductance/w-frequency (G/w–f) characteristics of Cd/CdS/n–Si/Au–Sb structures have been measured at the various biases 0.00–0.14 V at room temperature. The energy distribution of the interface states (N_ss) and their relaxation time (τ) have been determined from the forward bias capacitance–frequency characteristics. The N_ss and τ values have ranged from 2.01 × 10¹² cm⁻² eV⁻¹and 9.68 × 10⁻⁴ s in (Ec-0.45) eV–2.86 × 10¹³ cm⁻² eV⁻¹ and 3.81 × 10⁻⁴ s in (Ec-0.75) eV, respectively.     

Silicon MIS diodes with Cr2O3 nanofilm: Optical, morphological/structural and electronic transport properties

In this work we report the optical, morphological and structural characterization and diode application of Cr₂O₃ nanofilms grown on p-Si substrates by spin coating and annealing process. X-ray diffraction (XRD), non-contact mode atomic force microscopy (NC-AFM), ultraviolet-visible (UV-vis) spectroscopy and photoluminescence (PL) spectroscopy were used for characterization of nanofilms. For Cr₂O₃ nanofilms, the average particle size determined from XRD and NC-AFM measurements was approximately 70 nm. Structure analyses of nanofilms demonstrate that the single phase Cr₂O₃ on silicon substrate is of high a crystalline structure with a dominant in hexagonal (1 1 0) orientation. The morphologic analysis of the films indicates that the films formed from hexagonal nanoparticles are with low roughness and uniform. UV-vis absorption measurements indicate that the band gap of the Cr₂O₃ film is 3.08 eV. The PL measurement shows that the Cr₂O₃ nanofilm has a strong and narrow ultraviolet emission, which facilitates potential applications in future photoelectric nanodevices. Au/Cr₂O₃/p-Si metal/interlayer/semiconductor (MIS) diodes were fabricated for investigation of the electronic properties such as current-voltage and capacitance-voltage. Ideality factor and barrier height for Au//Cr₂O₃/p-Si diode were calculated as 2.15 eV and 0.74 eV, respectively. Also, interfacial state properties of the MIS diode were determined. The interface-state density of the MIS diode was found to vary from 2.90 × 10¹³ eV⁻¹ cm⁻² to 8.45 × 10¹² eV⁻¹ cm⁻².     

Low-temperature oxidation of SiGe by liquid-phase deposition

Low-temperature silicon dioxide (SiO₂) films were grown on silicon germanium (SiGe) surfaces using the liquid-phase deposition (LPD) method. The growth solutions of LPD-SiO₂ are hydrofluorosilicic acid (H₂SiF₆) and boric acid (H₃BO₃). It was found that the growth rate increases with increasing temperature and concentration of H₃BO₃. The Auger electron spectroscopy profile shows that no pileup of Ge atoms occurs at the interface of SiO₂/SiGe after the LPD-SiO₂ growth. Al/LPD-SiO₂/p-SiGe MOS capacitors were prepared to determine capacitance-voltage (C-V) and current-voltage (I-V) characteristics. In our experiments, a low leakage current density of 8.69 × 10⁻⁹ A/cm² under a 2 MV/cm electric field was observed. Such a value is much smaller than those of plasma- and thermal-oxides as a result of no plasma damage and a lower growth temperature. Moreover, lower oxide charges and interface charge densities of 3.82 × 10¹⁰ cm⁻² and 1.12 × 10¹¹ eV⁻¹ cm⁻², respectively, were achieved in our LPD-SiO₂ compared to direct photochemical-vapor-deposition-SiO₂.