考虑通孔横向热传输效应的三维集成电路热分析

考虑横向热传输效应,构造一种包含通孔结构的叠层芯片三维热传输模型.在具体的工艺参数下验证叠层芯片层数、通孔密度、通孔直径和后端线互连层厚度对三维集成电路热传输的影响.结果显示,采用该模型仿真得到的各层芯片温升要低于不考虑横向热传输时所得到的温升,差异最大可达10%以上,并且集成度要求越高,其横向热传输效应的影响越明显.该模型更符合实际情况,能够更准确地分析三维集成电路的各层芯片温度.     

考虑硅通孔的三维集成电路最高层温度模型

针对三维集成电路最高层芯片,引入硅通孔面积比例因子r,提出了考虑硅通孔的温度解析模型.Matlab分析表明,在芯片堆叠层数及芯片工作状态相同的情况下,考虑硅通孔之后的芯片温度比未考虑硅通孔时要低;r越大,芯片温度越低;当芯片堆叠层数较多且r较小时,温度随着r的减小急剧上升;对于8层的三维集成电路,硅通孔面积比例因子的最佳范围为0.5%~1%.     

三维集成电路堆叠硅通孔动态功耗优化

三维集成电路堆叠硅通孔结构具有良好的温度和热特性. 提出了一种协同考虑延时、面积与最小孔径的堆叠硅通孔动态功耗优化办法. 在提取单根硅通孔寄生电学参数的基础上, 分析了硅通孔的直径对多层硅通孔的功耗与延时性能的影响, 由此构建了分层逐级缩减堆叠硅通孔结构, 分析了硅通孔高度与氧化层厚度的影响. 结果表明, 该模型可在牺牲少许延时的情况下显著优化动态功耗, 在允许牺牲延时5%的情况下, 堆叠硅通孔的动态功耗最多可减少19.52%.     

一种考虑硅通孔电阻-电容效应的三维互连线模型

硅通孔(TSV)是三维集成电路的一种主流技术.基于TSV寄生参数提取模型,对不同物理尺寸的TSV电阻-电容(RC)参数进行提取,采用Q3D仿真结果验证了模型精度.分析TSVRC效应对片上系统的性能及功耗影响,推导了插入缓冲器的三维互连线延时与功耗的解析模型.在45nm互补金属氧化物半导体工艺下,对不同规模的互连电路进行了比较分析.模拟结果显示,TSVRC效应导致互连延时平均增加10%,互连功耗密度平均提高21%;电路规模越小,TSV影响愈加显著.在三维片上系统前端设计中,包含TSV寄生参数的互连模型将有助于设计者更加精确地预测片上互连性能.     

量子电容对CNT填充的屏蔽型TSV的传输性能影响研究

本文提出以苯并环丁烯(benzocyclobutene,BCB)或硅为介质层材料,用碳纳米管(Carbon Nanotube,CNT)填充的屏蔽型硅通孔(Shielded Through-Silicon Vias,S-TSV)结构,利用等效传输线模型计算了其正向传输系数和衰减常数,分析了量子电容(Quantum Capacitance,Cq)对S-TSV传输性能的影响。研究发现,Cq能改善以BCB为介质层,填充多壁碳纳米管束(Multi-walled carbon nanotube bundle,MWCNTB)的S-TSV高于20GHz频段的传输性能。此外,Cq可以明显提升以硅为介质层的S-TSV的传输性能,且Cq的温度效应能与硅电导的温度效应平衡,从而提高S-TSV的热稳定性。     

考虑通孔和边缘效应的互连网络热电分析

考虑互连通孔和边缘效应,建立互连层间、层内、通孔热阻模型,利用热电二元性,提出一种考虑温度效应对热流影响的热电耦合仿真方法,利用热电之间的反馈关系,修正建模后的温度分布对节点网络热流的影响.并对以聚合物和硅氧化物为介质的多层互连进行分析,以有限元建模结果为参照,与已有模型相比,互连热分布结果的相对标准差分别降低了71.2%、12.9%.考虑通孔效应和边缘效应后,该方法在不同纳米级工艺中所得峰值温升,较已有模型均有一定程度的降低.     

单晶生长炉全局热分析(1)——三维模型建立

晶体生长炉内高温热辐射和熔液对流十分复杂,使分析整个生长炉内传输现象的全局热分析模型一直停留在轴对称准静态假定上.本文考虑熔液对流的三维性和非定常性,构筑了三维全局热分析模型,讨论了熔液对流三维性和非定常性的影响.结果表明:本文模型预测的晶体成长界面反转临界雷诺数大大降低,更接近实际.     

基于对偶单元法的三维集成微系统电热耦合分析

随着三维集成微系统集成度和功率密度的提高,同时考察电设计与热管理的多场耦合分析势在必行.本文面向三维集成微处理器系统,通过改进的对偶单元法(dual cell method,DCM)实现了系统的快速电热分析.该方法通过引入泄漏功率、材料系数随温度的耦合,相比于传统有限元法在更新以及组装本构矩阵上有更大的优势.仿真验证表明,本文所采用的算法相比传统有限元法仿真速度提升了约30%.在考虑了材料系数以及泄露功率热耦合因素后,系统热点温度相对于考虑耦合前上升了20.8 K.最后采用本文所提出算法对三维集成微处理器系统进行布局研究,比较了硅通孔阵列常规布局和集中布局在处理器核心下方两种布局方式对上下层芯片热点温度的影响,研究了功率不均匀分配对两种布局的影响.     

高功率激光器窗口三维温度场分析及其热透镜研究

对高功率激光器输出耦合镜的受热情况进行了分析,在实际工作模型下 设定了圆柱坐标下的热传导方程边界条件。对高功率激光器输出耦合镜所处的物理状态进行了符合实际情况的简化,求得了热传导方程的解析解。对GaAs窗口材料分析了高功率激光器输出耦合镜内部温度分布,在考虑了材料折射率与线膨胀系数随温度变化的因素后,计算了等效光程变化及其引起的热透镜效应。     

采用不同辐射换热模型对液氦传输管线的数值研究

低温传输管线是大型低温制冷设备中的关键部件之一,采用高真空多层绝热方式减少低温传输管线的漏热。基于Fluent计算平台,分别采用DTRM模型、P1模型、ROSSELAND模型、DO模型、S2S模型对真空环境下的液氦传输管线进行了数值模拟。对比解析计算解,确定了适合液氦低温管真空环境下辐射换热的计算模型,并利用S2S模型对低温传输管线的整体结构进行了模拟。模拟分析表明:S2S模型计算得到的管壁面辐射和温度场与解析解较为接近,更适合真空环境下的壁面辐射换热计算;支撑漏热为主要漏热,管壁面间辐射换热占总漏热量比例较小,整体漏热小于1W/m,满足设计需求。     

Through-silicon-via crosstalk model and optimization design for three-dimensional integrated circuits

Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 rnV and 379 mV reductions in the peak noise voltage, respectively.     

An analytical model of thermal mechanical stress induced by through silicon via

We present an accurate through silicon via(TSV) thermal mechanical stress analytical model which is verified by using finite element method(FEM). The results show only a very small error. By using the proposed analytical model, we also study the impacts of the TSV radius size, the thickness, the material of Cu diffusion barrier, and liner on the stress. It is found that the liner can absorb the stress effectively induced by coefficient of thermal expansion mismatch. The stress decreases with the increase of liner thickness. Benzocyclobutene(BCB) as a liner material is better than Si O2. However,the Cu diffusion barrier has little effect on the stress. The stress with a smaller TSV has a smaller value. Based on the analytical model, we explore and validate the linear superposition principle of stress tensors and demonstrate the accuracy of this method against detailed FEM simulations. The analytic solutions of stress of two TSVs and three TSVs have high precision against the finite element result.     

Stress evaluation of Through-Silicon Vias using micro-infrared photoelasticity and finite element analysis

The Through-SiliconVias (TSV) is a key component of three dimensional electronic packaging. Obtaining its stresses is very important for evaluating its reliability. A micro-infrared photoelasticity system with a thermal loading function was built and applied to characterize the stresses of the TSV structure. Through testing it was found that the stress of each TSV is different even if their fabrication technology is exactly the same, that different TSVs obtain their stress free states at different elevated temperatures, and that their stress free states are maintained even when the temperature is further elevated. A finite element model was used to quantitatively determine the stresses of a TSV under different stress-free temperatures. Different virtual photoelasticity fringe patterns were then created based on the principle of photoelasticity and the simulated stresses. Comparing the virtual fringe patterns with the experimental pattern, an appropriate virtual photoelasticity fringe pattern and the corresponding stresses of TSV were determined     

Investigation of thermal effects in through-silicon vias using scanning thermal microscopy

Results of quantitative investigations of copper through-silicon vias (TSVs) are presented. The experiments were performed using scanning thermal microscopy (SThM), enabling highly localized imaging of thermal contrast between the copper TSVs and the surrounding material. Both dc and ac active-mode SThM was used and differences between these variants are shown. SThM investigations of TSVs may provide information on copper quality in TSV, as well as may lead to quantitative investigation of thermal boundaries in micro- and nanoelectronic structures. A proposal for heat flow analysis in a TSV, which includes the influence of the boundary region between the TSV and the silicon substrate, is presented; estimation of contact resistance and boundary thermal conductance is also given.     

Three-dimensional global interconnect based on a design window

Based on a stochastic wire length distributed model, the interconnect distribution of a three-dimensional integrated circuit (3D IC) is predicted exactly. Using the results of this model, a global interconnect design window for a giga-scale system-on-chip (SOC) is established by evaluating the constraints of 1) wiring resource, 2) wiring bandwidth, and 3) wiring noise. In comparison to a two-dimensional integrated circuit (2D IC) in a 130-nm and 45-nm technology node, the design window expands for a 3D IC to improve the design reliability and system performance, further supporting 3D IC application in future integrated circuit design.