An Improved Design of n-Bit Universal Reversible Gate Library

Reversible logic has been considered as an important solution to the power dissipation problem in the existing electronic devices. Many universal reversible libraries that include more than one type of gates have been proposed in the literature. This paper proposes a novel reversible n-bit gate that is proved to be universal for synthesizing reversible circuits. Reducing the reversible circuit synthesis problem to permutation group allows Schreier-Sims Algorithm for the strong generating set-finding problem to be used in the synthesize of reversible circuits using the proposed gate. A novel optimization rules will be proposed to further optimize the synthesized circuits in terms of the number of gates, the quantum cost and the utilization of library to achieve better results than that shown in the literature.

     

Effective Designs of Reversible Vedic Multiplier

Power dissipation problem is one of the most challenging problems in designing conventional electronic circuits. One of the best approaches to overcome this problem is to design reversible circuits. Nowadays, reversible logic is considered as a new field of study that has various applications such as optical information processing, design of low power CMOS circuits, quantum computing, DNA computations, bioinformatics and nanotechnology. Due to the vulnerability of the digital circuits to different environmental factors, the design of circuits with error-detection capability is considered a necessity. Parity preserving technique is known as one of the most famous methods for providing error-detection ability. Multiplication operation is considered as one of the most important operations in computing systems, which can play a significant role in increasing the efficiency of such systems. In this paper, two efficient 4-bit reversible multipliers are proposed using the Vedic technique. The Vedic technique is able to increase the speed of multiplication operation by producing partial products and their sums simultaneously in a parallel manner. The first architecture lacks the parity preserving potential, while the second architecture has the ability parity preserving. Since a 4-bit Vedic multiplier includes 2-bit Vedic multipliers and 4-bit ripple carry adders (RCA), so in the first design, TG, PG and FG gates have been used to design an efficient 2-bit reversible Vedic multiplier, as well as PG gate and HNG block have been applied as a half-adder (HA) and full-adder (FA) in the 4-bit RCAs. Also, in the second design, 2-bit parity preserving reversible Vedic multiplier has been designed using FRG, DFG, ZCG and PPTG gates as well as ZCG and ZPLG blocks have been utilized as HA and FA in the 4-bit RCAs. Proposed designs are compared in terms of evaluation criteria of circuits such as gate count (GC), number of constant inputs (CI), number of garbage outputs (GO), quantum cost (QC), and hardware complexity. The results of the comparisons indicate that the proposed designs are more efficient compared to available counterparts.

     

Quantum Circuit Synthesis using a New Quantum Logic Gate Library of NCV Quantum Gates

Since Controlled-Square-Root-of-NOT (CV, CV^?) gates are not permutative quantum gates, many existing methods cannot effectively synthesize optimal 3-qubit circuits directly using the NOT, CNOT, Controlled-Square-Root-of-NOT quantum gate library (NCV), and the key of effective methods is the mapping of NCV gates to four-valued quantum gates. Firstly, we use NCV gates to create the new quantum logic gate library, which can be directly used to get the solutions with smaller quantum costs efficiently. Further, we present a novel generic method which quickly and directly constructs this new optimal quantum logic gate library using CNOT and Controlled-Square-Root-of-NOT gates. Finally, we present several encouraging experiments using these new permutative gates, and give a careful analysis of the method, which introduces a new idea to quantum circuit synthesis.     

Quaternary Quantum/Reversible Half-Adder,Full-Adder,Parallel Adder and Parallel Adder/Subtractor Circuits

Multiple valued quantum logic is a promising research area in quantum computing technology having several advantages over binary quantum logic. Adder circuits as well as subtractor circuits are the major components of various computational units in computers and other complex computational systems. In this paper, we propose a quaternary quantum reversible half-adder circuit using quaternary 1-qudit gates, 2-qudit Feynman and Muthukrishnan-Stroud gates. Then we propose a quaternary quantum reversible full adder and a quaternary quantum parallel adder circuit. In addition, we propose a quaternary quantum reversible parallel adder/subtractor circuit. The proposed designs are compared with existing designs and improvements in terms of hardware complexity, quantum cost, number of constant inputs and garbage outputs are reported.

     

An Efficient Design of Reversible Multi-Bit Quantum Comparator Via Only a Single Ancillary Bit

Quantum computing has emerged as one of the most promising technology due to its powerful computing capability. And quantum basic circuits like quantum comparator, quantum adder etc, are the foundation to realize quantum computing. In this paper, we present an efficient design to realize the comparison of two n-bit quantum logic states via only a single ancillary bit. Our proposed comparator compares two n-bit quantum logic states and identifies which of them is the largest, which of them is the smallest, and which of them is equal in linear quantum depth. Moreover, we analyze the superior performance of our proposed comparator in terms of auxiliary bits compared with the existing quantum logic comparators.     

Design of Ultra-Efficient Reversible Gate Based 1-bit Full Adder in QCA with Power Dissipation Analysis

The difficulties which the CMOS technology is facing at the nano scale has led to the investigation of quantum-dot cellular automata (QCA) nanotechnology and reversible logic as an alternative to conventional CMOS technology. In this paper, these two paradigms have been combined. Firstly, a new 3 × 3 reversible gate, SSG-QCA, which is universal and multifunctional in nature, is proposed and implemented in QCA using conventional 3-input majority voter based logic. By using the concept of explicit interaction of cells, the proposed gate is further optimized and then used to design an ultra-efficient 1-bit full adder in QCA. The universal nature has been verified by designing all the logic gates from the proposed SSG-QCA gate whereas the multifunctional nature is verified by implementing all the 13 standard Boolean functions. The proposed 3 × 3 gate and adder designs are then extensively compared with the existing literature and it is observed that the proposed designs are ultra-efficient in terms of both area and cost in QCA technology. In addition to this energy dissipation analysis for different scenarios is also done on all the designs and it is observed that the proposed designs dissipate minimum energy thereby making them suitable for ultra-low power designs.

     

Designing Nanoscale Counter Using Reversible Gate Based on Quantum-Dot Cellular Automata

Some new technologies such as Quantum-dot Cellular Automata (QCA) is suggested to solve the physical limits of the Complementary Metal-Oxide Semiconductor (CMOS) technology. The QCA as one of the novel technologies at nanoscale has potential applications in future computers. This technology has some advantages such as minimal size, high speed, low latency, and low power consumption. As a result, it is used for creating all varieties of memory. Counter circuits as one of the important circuits in the digital systems are composed of some latches, which are connected to each other in series and actually they count input pulses in the circuit. On the other hand, the reversible computations are very important because of their ability in reducing energy in nanometer circuits. Improving the energy efficiency, increasing the speed of nanometer circuits, increasing the portability of system, making smaller components of the circuit in a nuclear size and reducing the power consumption are considered as the usage of reversible logic. Therefore, this paper aims to design a two-bit reversible counter that is optimized on the basis of QCA using an improved reversible gate. The proposed reversible structure of 2-bit counter can be increased to 3-bit, 4-bit and more. The advantages of the proposed design have been shown using QCADesigner in terms of the delay in comparison with previous circuits.     

Mach-Zehnder interferometer-based all-optical reversible logic gate

In recent years, reversible logic has emerged as a promising computing paradigm having application in low-power CMOS, quantum computing, nanotechnology and optical computing. Optical logic gates have the potential to work at macroscopic (light pulses carry information), or quantum (single photons carry information) levels with great efficiency. However, relatively little has been published on designing reversible logic circuits in all-optical domain. In this paper, we propose and design a novel scheme of Toffoli and Feynman gates in all-optical domain. We have described their principle of operations and used a theoretical model to assist this task, finally confirming through numerical simulations. Semiconductor optical amplifier (SOA)-based Mach-Zehnder interferometer (MZI) can play a significant role in this field of ultra-fast all-optical signal processing. The all-optical reversible circuits presented in this paper will be useful to perform different arithmetic (full adder, BCD adder) and logical (realization of Boolean function) operations in the domain of reversible logic-based information processing.     

飞秒激光直写光量子逻辑门

量子比特在同一时刻可处于所有可能状态上的叠加特性使得量子计算机具有天然的并行计算能力,在处理某些特定问题时具有超越经典计算机的明显优势.飞秒激光直写技术因其具有单步骤高效加工真三维光波导回路的能力,在制备通用型集成光量子计算机的基本单元—量子逻辑门中发挥着越来越重要的作用.本文综述了飞秒激光直写由定向耦合器构成的光量子比特逻辑门的进展.主要包括定向耦合器的功能、构成、直写和性能表征,集成波片、哈达玛门和泡利交换门等单量子比特逻辑门、受控非门和受控相位门等两量子比特逻辑门的直写加工,并对飞秒激光加工三量子比特逻辑门进行了展望.     

Quantum Fourier Transform-Based Arithmetic Logic Unit on a Quantum Processor

This study proposes and construct a primitive quantum arithmetic logic unit (qALU) based on the quantum Fourier transform (QFT). The qALU is capable of performing arithmetic ADD (addition) and logic NAND gate operations. It designs a scalable quantum circuit and presents the circuits for driving ADD and NAND operations on two-input and four-input quantum channels, respectively. By comparing the required number of quantum gates for serial and parallel architectures in executing arithmetic addition, it evaluates the performance. It also execute the proposed quantum Fourier transform-based qALU design on real quantum processor hardware provided by IBM. The results demonstrate that the proposed circuit can perform arithmetic and logic operations with a high success rate. Furthermore, it discusses in detail the potential implementations of the qALU circuit in the field of computer science, highlighting the possibility of constructing a soft-core processor on a quantum processing unit.     

Optically implementable designs of reversible sequential devices

We have proposed some new designs of reversible sequential circuits using NCT gate library and compared them with the earlier proposals. It has been shown that the present proposals have lower gate complexities and lower number of garbage bits compared to the earlier proposals. We have addressed some conceptual issues related to the feedback and the choice of gate library. Further it is shown that the proposed quantum / reversible circuits can be implemented optically.     

Shannon Logic Based Novel QCA Full Adder Design with Energy Dissipation Analysis

Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology to replace VLSI-CMOS digital circuits. Due to its attractive features such as low power consumption, ultra-high speed switching, high device density, several digital arithmetic circuits have been proposed. Adder circuit is the most prominent component used for arithmetic operations. All other arithmetic operation can be successively performed using adder circuits. This paper presents Shannon logic based QCA efficient full adder circuit for arithmetic operations. Shannon logic expression with control variables helps the designer to reduce hardware cost; using with minimum foot prints of the chip size. The mathematical models of the proposed adder are verified with the theoretical values. In addition, the energy dissipation losses of the proposed adder are carried out. The energy dissipation calculation is evaluated under the three separate tunneling energy levels, at temperature T = 2K.The proposed adder dissipates less power. QCAPro tool is used for estimating the energy dissipation. In this paper we proposed novel Shannon based adder for arithmetic calculations. This adder has been verified in different aspects like using Boolean algebra besides it power analysis has been calculated. In addition 1-bit full adder has been enhanced to propose 2-bit and 4-bit adder circuits.     

利用非稳定子态容错实现密集旋转操作

Non-Clifford操作不能在量子纠错码上自然横向实现, 但可通过辅助量子态和在量子纠错码上能横向实现的Clifford操作来容错实现, 从而取得容错量子计算的通用性. 非平庸的单量子比特操作是Non-Clifford操作, 可以分解为绕z轴和绕x轴非平庸旋转操作的组合. 本文首先介绍了利用非稳定子态容错实现绕z轴和绕x轴旋转的操作, 进而设计线路利用魔幻态容错制备非稳定子态集, 最后讨论了运用制备的非稳定子态集模拟任意非平庸单量子比特操作的问题. 与之前工作相比, 制备非稳定子态的线路得到简化, 成功概率提高, 且在高精度模拟任意单量子比特操作时所消耗的非稳定子态数目减少了50%. 关键词： 容错量子计算 非稳定子态 魔幻态 Clifford操作     

Modular Adder Designs Using Optimal Reversible and Fault Tolerant Gates in Field-Coupled QCA Nanocomputing

The challenges which the CMOS technology is facing toward the end of the technology roadmap calls for an investigation of various logical and technological solutions to CMOS at the nano scale. Two such paradigms which are considered in this paper are the reversible logic and the quantum-dot cellular automata (QCA) nanotechnology. Firstly, a new 3 × 3 reversible and universal gate, RG-QCA, is proposed and implemented in QCA technology using conventional 3-input majority voter based logic. Further the gate is optimized by using explicit interaction of cells and this optimized gate is then used to design an optimized modular full adder in QCA. Another configuration of RG-QCA gate, CRG-QCA, is then proposed which is a 4 × 4 gate and includes the fault tolerant characteristics and parity preserving nature. The proposed CRG-QCA gate is then tested to design a fault tolerant full adder circuit. Extensive comparisons of gate and adder circuits are drawn with the existing literature and it is envisaged that our proposed designs perform better and are cost efficient in QCA technology.     

Modified Khaneja--Glaser Decomposition and Realization of Three-Qubit Quantum Gate

Optimal implementation of quantum gates is crucial for realization of quantum computation. We slightly modify the Khaneja-Glaser decomposition （KGD） for n-qubits and give a new Cartan subalgbra in the second step of the decomposition. Based on this modified KGD, we investigate the realization of three-qubit logic gate and obtain the result that a general three-qubit quantum logic gate can be implemented using at most 73 one-qubit gates rotations with respect to the y and z axes and 26 CNOT gates.     

Universal quantum control based on parametric modulation in superconducting circuits

As superconducting quantum circuits are scaling up rapidly towards the noisy intermediate-scale quantum(NISQ)era, the demand for electronic control equipment has increased significantly. To fully control a quantum chip of N qubits,the common method based on up-conversion technology costs at least 2 × N digital-to-analog converters(DACs) and N IQ mixers. The expenses and complicate mixer calibration have become a hinderance for intermediate-scale quantum control.Here we propose a universal control scheme for superconducting circuits, fully based on parametric modulation. To control N qubits on a chip, our scheme only requires N DACs and no IQ mixer, which significantly reduces the expenses. One key idea in the control scheme is to introduce a global pump signal for single-qubit gates. We theoretically explain how the universal gates are constructed using parametric modulation. The fidelity analysis shows that parametric single-qubit(two-qubit) gates in the proposed scheme can achieve low error rates of 10~(4), with a gate time of about 60 ns(100 ns).     

III–V quantum devices and circuits based on nanoscale Schottky gate control of hexagonal quantum wire networks

The concept, the present status, key issues and future prospects of a novel hexagonal binary decision diagram (BDD) quantum circuit approach for III–V quantum large-scale integrated circuits (QLSIs) are presented and discussed. In this approach, the BDD logic circuits are implemented on III–V semiconductor-based hexagonal nanowire networks controlled by nanoscale Schottky gates. The hexagonal BDD QLSIs can operate at delay-power products near the quantum limit in the quantum regime as well as in the many-electron classical regime. To demonstrate the feasibility of the present approach, GaAs Schottky wrap gate (WPG)-based single-electron BDD node devices and their integrated circuits were fabricated and their proper operations were confirmed. Selectively grown InGaAs sub-10 nm quantum wires and their hexagonal networks have been investigated to form high-density hexagonal BDD QLSIs operating in the quantum regime at room temperature.     

Shortcut-based quantum gates on superconducting qubits in circuit QED

Construction of optimal gate operations is significant for quantum computation. Here an efficient scheme is proposed for performing shortcut-based quantum gates on superconducting qubits in circuit quantum electrodynamics (QED). Two four-level artificial atoms of Cooper-pair box circuits, having sufficient level anharmonicity, are placed in a common quantized field of circuit QED and are driven by individual classical microwaves. Without the effect of cross resonance, one-qubit NOT gate and phase gate in a decoupled atom can be implemented using the invariant-based shortcuts to adiabaticity. With the assistance of cavity bus, a one-step SWAP gate can be obtained within a composite qubit-photon-qubit system by inversely engineering the classical drivings. We further consider the gate realizations by adjusting the microwave fields. With the accessible decoherence rates, the shortcut-based gates have high fidelities. The present strategy could offer a promising route towards fast and robust quantum computation with superconducting circuits experimentally.