Dipole formation and electrical properties of high-k/SiO2 interface according to the density of SiO2 interfacial layer

The effect of SiO₂ buffer layers with various atomic densities on the interface dipole of high-k/SiO₂ is confirmed. An ultrathin SiO₂ layer is formed on Si using the plasma-enhanced chemical vapor deposition (PECVD), H₂O₂ oxidation and nitric acid oxidation (NAOS). The atomic density ratio between the SiO₂ layer with various methods and the high-k is calculated respectively. As the oxygen density of the SiO₂ increased, the amount of the dipole and the flatband voltage (V_FB) shift decreased. Furthermore, leakage current density of the H₂O₂ (0.9 × 10⁻² A/cm²) due to the formation of low-density SiO₂, decreases by approximately six orders of magnitude when SiO₂ buffer layer is inserted using the NAOS (5.13 × 10^-8 A/cm²). Consequently, it is demonstrated that the dipoles that affects the V_FB shift is formed by the diffusion of oxygen ions between the high-k and SiO₂ interface, which has a significant effect of the MOS capacitor.     

Evidence of GeO volatilization and its effect on the characteristics of HfO2 grown on Ge substrate

HfO₂ films are deposited by atomic layer deposition (ALD) using tetrakis ethylmethylamino hafnium (TEMAH) as the hafnium precursor, while O₃ or H₂O is used as the oxygen precursor. After annealing at 500℃ in nitrogen, the thickness of Ge oxide's interfacial layer decreases, and the presence of GeO is observed at the H₂O-based HfO₂ interface due to GeO volatilization, while it is not observed for the O₃-based HfO₂. The difference is attributed to the residue hydroxyl groups or H₂O molecules in H₂O-based HfO₂ hydrolyzing GeO₂ and forming GeO, whereas GeO is only formed by the typical reaction mechanism between GeO₂ and the Ge substrate for O₃-based HfO₂ after annealing. The volatilization of GeO deteriorates the characteristics of the high-κ films after annealing, which has effects on the variation of valence band offset and the C–V characteristics of HfO₂/Ge after annealing. The results are confirmed by X-ray photoelectron spectroscopy (XPS) and electrical measurements.     

High-k Al2O3 MOS structures with Si interface control layer formed on air-exposed GaAs and InGaAs wafers

This paper attempts to realize unpinned high-k insulator-semiconductor interfaces on air-exposed GaAs and In_0.53Ga_0.47As by using the Si interface control layer (Si ICL). Al₂O₃ was deposited by ex situ atomic layer deposition (ALD) as the high-k insulator. By applying an optimal chemical treatment using HF acid combined with subsequent thermal cleaning below 500 °C in UHV, interface bonding configurations similar to those by in situ UHV process were achieved both for GaAs and InGaAs after MBE growth of the Si ICL with no trace of residual native oxide components. As compared with the MIS structures without Si ICL, insertion of Si ICL improved the electrical interface quality, a great deal both for GaAs and InGaAs, reducing frequency dispersion of capacitance, hysteresis effects and interface state density (D_it). A minimum value of D_it of 2 × 10¹¹ eV⁻¹ cm⁻² was achieved both for GaAs and InGaAs. However, the range of bias-induced surface potential excursion within the band gap was different, making formation of electron layer by surface inversion possible in InGaAs, but not possible in GaAs. The difference was explained by the disorder induced gap state (DIGS) model.     

Characteristics improvement of HfO2/Ge gate stack structure by fluorine treatment of germanium surface

Chemical reactivity of fluorine molecule (F₂)-germanium (Ge) surface and dissociation of fluorine (F)-Ge bonding have been simulated by semi-empirical molecular orbital method theoretically, which shows that F on Ge surface is more stable compared to hydrogen. Ge MIS (metal insulator semiconductor) capacitor has been fabricated by using F₂-treated Ge(1 0 0) substrate and HfO₂ film deposited by photo-assisted MOCVD. Interface state density observed as a hump in the C-V curve of HfO₂/Ge gate stack and its C-V hysteresis were decreased by F₂-treatment of Ge surface. XPS (X-ray photoelectron spectroscopy) depth profiling reveals that interfacial layer between HfO₂ and Ge is sub-oxide layer (GeO_x or HfGeO_x), which is believed to be origin of interface state density.F was incorporated into interfacial layer easily by using F₂-treated Ge substrate. These results suggest that interface defect of HfO₂/Ge gate stack structure could be passivated by F effectively.     

Growth and interfacial properties of atomic layer deposited Al0.7Ti0.3O y high-k dielectric on Ge substrate

Growth and interfacial properties of atomic layer deposited Al_0.7Ti_0.3O _y on Ge have been investigated as a potential high-k gate dielectric for future Ge-based metal oxide semiconductor devices. A sandwich structure of Al₂O₃/TiO₂ stack is proposed for Al₂O₃/TiO₂ intermixing and high-k/Ge interfacial passivation. The film thicknesses and interface microstructure are characterized by spectroscopy ellipsometry and high-resolution transmission electron microscopy. X-ray photoelectron spectrometry is used to analyze the chemical composition and bonding states, and to reveal the band alignment of high-k/Ge heterojunctions. Metal-oxide-capacitors are formed by depositing aluminum electrodes to perform capacitance–voltage measurements for electrical characteristics. All evidences show a positive prospect of employing atomic layer deposited Al_0.7Ti_0.3O _y as high-k gate dielectric for future Ge-based devices.     

Ge metal oxide semiconductor field effect transistors with optimized Si cap and HfSiO2 high-k metal gate stacks

High mobility metal-oxide-semiconductor-field-effect-transistors (MOSFETs) are demonstrated on high quality epitaxial Si_0.75Ge_0.25 films selectively grown on Si (100) substrates. With a Si cap processed on Si_0.75Ge_0.25 channels, HfSiO₂ high-k gate dielectrics exhibited low C–V hysteresis (<10 mV), interface trap density (7.5 × 10¹⁰), and gate leakage current (∼10⁻²A/cm² at an EOT of 13.4 Å), which are comparable to gate stack on Si channels. The mobility enhancement afforded intrinsically by the Si_0.75Ge_0.25 channel (60%) is further increased by a Si cap (40%) process, resulting in a combined ∼100% enhancement over Si channels. The Si cap process also mitigates the low potential barrier issues of Si_0.75Ge_0.25 channels, which are major causes of the high off-state current of small band gap energy Si_0.75Ge_0.25 pMOSFETs, by improving gate control over the channel.     

Probing buried interfaces on Ge-based metal gate/high-k stacks by hard X-ray photoelectron spectroscopy

In this contribution, we present results of a non-destructive in-depth analysis of concentration of chemical components at buried interfaces on Ge-based CMOS by means of hard X-ray photoelectron spectroscopy (HAXPES) and low angle X-ray reflectivity (XRR). Two samples composed of a Ge/Si/SiO₂/HfO₂/TiN stack, with layer and interlayer thicknesses of 2500, 0.9, 0.5, 4.9, 3.4 nm and 2500, 0.7, 1, 5.8, 3 nm have been studied. The use of electrons with kinetic energies from few eV up to 15 keV enables to tune the information depth being able to analyze the desired interface in a non-destructive way. XRR enables the determination of the exact layer thickness and density. The results suggest that the Si interlayer prevents the Ge oxidation. Depth profiles of the electronic structure have been obtained for both samples by following the evolution of the photoemission signal from the Hf 2p_3/2 core level as a function of the photoelectron kinetic energy. The depth profile of the electronic structure reveals the presence of a chemical shift of the Hf 2p_3/2 core level, which is related to an interfacial bonding state. Our results demonstrate the excellent capability of HAXPES to study buried interfaces in a non-destructive way.     

Interactions of germanium atoms with silica surfaces

GeH₄ is thermally cracked over a hot filament depositing 0.7-15 ML Ge onto 2-7 nm SiO₂/Si(1 0 0) at substrate temperatures of 300-970 K. Ge bonding changes are analyzed during annealing with X-ray photoelectron spectroscopy. Ge, GeH_x, GeO, and GeO₂ desorption is monitored through temperature programmed desorption in the temperature range 300-1000 K. Low temperature desorption features are attributed to GeO and GeH₄. No GeO₂ desorption is observed, but GeO₂ decomposition to Ge through high temperature pathways is seen above 750 K. Germanium oxidization results from Ge etching of the oxide substrate. With these results, explanations for the failure of conventional chemical vapor deposition to produce Ge nanocrystals on SiO₂ surfaces are proposed.     

Swift ion irradiation effect on high-k ZrO2- and Al2O3-based MOS devices

This paper describes the heavy ion-induced effects on the electrical characteristics of reactively sputtered ZrO₂ and Al₂O₃ high-k gate oxides deposited in argon plus nitrogen containing plasma. Radiation-induced degradation of sputtered high-k dielectric ZrO₂/Si and Al₂O₃/Si interface was studied using 45?MeV Li³⁺ ions. The devices were irradiated with Li³⁺ ions at various fluences ranging from 5?×?10⁹ to 5?×?10¹²?ions/cm². Capacitance–voltage and current–voltage characteristics were used for electrical characterization. Shift in flat band voltage towards negative value was observed in devices after exposure to ion radiation. Post-deposition annealing effect on the electrical behavior of high-k/Si interface was also investigated. The annealed devices showed better electrical and reliability characteristics. Different device parameters such as flat band voltage, leakage current, interface defect density and oxide-trapped charge have been extracted.The surface morphology and roughness values for films deposited in nitrogen containing plasma before and after ion radiation are extracted from Atomic Force Microscopy.     

Electrical characterization studies of p-type Ge,Ge1−ySny,and Si0.09Ge0.882Sn0.028 grown on n-Si substrates

The electrical properties of p-type Ge, Ge_1−ySn_y, and Si_0.09Ge_0.882Sn_0.028 samples grown on n-type Si substrates using ultra-high vacuum chemical vapor deposition have been investigated as a function of temperature. Degenerate parallel conducting layers were found in all Ge/Si, Ge_1−ySn_y/Si, and Si_0.09Ge_0.882Sn_0.028/Si samples, which are believed to be associated with dislocation defects at the interface produced by the lattice mismatch between the two materials. These degenerate conducting layers affect the electrical properties of all the thin epitaxial films. Additionally, temperature dependent Hall-effect measurements show that these materials exhibit a conductivity type change from p to n at around 370–435 K. The mobilities of these samples are generally lower than that of bulk Ge due to carrier scattering near the interface between the epitaxial layer and the Si substrate and also due to alloy scattering. Detailed behavior of temperature-dependent conductivity of these samples is also discussed.     

Study of the component distribution in Si/GexSi1−x /Si heterostructures grown by molecular beam epitaxy

This paper reports on a study of the depth profile of components in GeSi heterostructures grown on low-temperature silicon (LTSi: T _gr ～ 350–400° C) and porous silicon by molecular-beam epitaxy. An excess Ge concentration was found by Auger electron spectroscopy depth profiling at the Ge_xSi_1?x /LTSi interface, which decreased in all samples subjected to annealing. The Ge diffusion activation energy was calculated to be E _a ≈ 1.6 eV in this case. An enhanced Ge concentration was also detected by x-ray photoelectron spectroscopy at the Si cap surface. Possible reasons for the surface enrichment of the silicon layer and of the Ge_xSi_1?x film interface by germanium are considered, and the relation between the component distribution and the structural features of plastically strain-relieved layers are discussed.     

Structural and electrical properties of a high-k SmAlO3 charge trapping flash memory

In this study, we proposed the Al/Al₂O₃/SmAlO₃/SiO₂/Si flash memory devices using high-k SmAlO₃ film as a charge trapping layer and high-k Al₂O₃ film as a blocking layer. The structural and morphological features of these films were explored by X-ray diffraction, X-ray photoelectron spectroscopic and atomic force microscopy. The SmAlO₃ flash memory devices annealed at 800 °C showed excellent electrical properties, such as a large memory window of ～2.61 V (measured at a sweep voltage range of ±5 V) and a small charge loss of ～7.1% (measured time up to 10⁴ s). In addition, the charge trap centroid and charge trap density were extracted by constant current stress method.     

Trap-controlled behavior in ultrathin Lu2O3 high-k gate dielectrics

Amorphous Lu₂O₃ high-k gate dielectrics were grown directly on n-type (100) Si substrates by the pulsed laser deposition (PLD) technique. High-resolution transmission electron microscope (HRTEM) observation illustrated that the Lu₂O₃ film has amorphous structure and the interface with Si substrate is free from amorphous SiO₂. An equivalent oxide thickness (EOT) of 1.1 nm with a leakage current density of 2.6×10⁻⁵ A/cm² at 1 V accumulation bias was obtained for 4.5 nm thick Lu₂O₃ thin film deposited at room temperature followed by post-deposition anneal (PDA) at 600 °C in oxygen ambient. The effects of PDA process and light illumination were studied by capacitance-voltage (C-V) and current density-voltage (J-V) measurements. It was proposed that the net fixed charge density and leakage current density could be altered significantly depending on the post-annealing conditions and the capability of traps to trap and release charges.     

Interface engineering with an MOCVD grown ZnO interface passivation layer for ZrO2-GaAs metal-oxide-semiconductor devices

This work deals with the fabrication of a GaAs metal-oxide-semiconductor device with an unpinned interface environment. An ultrathin (∼2 nm) interface passivation layer (IPL) of ZnO on GaAs was grown by metal organic chemical vapor deposition to control the interface trap densities and to prevent the Fermi level pinning before high-k deposition. X-ray photoelectron spectroscopy and high resolution transmission electron microscopy results show that an ultra thin layer of ZnO IPL can effectively suppress the oxides formation and minimize the Fermi level pinning at the interface between the GaAs and ZrO₂. By incorporating ZnO IPL, GaAs MOS devices with improved capacitance-voltage and reduced gate leakage current were achieved. The charge trapping behavior of the ZrO₂/ZnO gate stack under constant voltage stressing exhibits an improved interface quality and high dielectric reliability.     

Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications

This work covers the impact of dual metal gate engineered Junctionless MOSFET with various high-k dielectric in Nanoscale circuits for low power applications. Due to gate engineering in junctionless MOSFET, graded potential is obtained and results in higher electron velocity of about 31% for HfO₂ than SiO₂ in the channel region, which in turn improves the carrier transport efficiency. The simulation is done using sentaurus TCAD, ON current, OFF current, I_ON/I_OFF ratio, DIBL, gain, transconductance and transconductance generation factor parameters are analysed. When using HfO₂, DIBL shows a reduction of 61.5% over SiO₂. The transconductance and transconductance generation factor shows an improvement of 44% and 35% respectively. The gain and output resistance also shows considerable improvement with high-k dielectrics. Using this device, inverter circuit is implemented with different high-k dielectric material and delay have been decreased by 4% with HfO₂ when compared to SiO₂. In addition, a significant reduction in power dissipation of the inverter circuit is obtained with high-k dielectric Dual Metal Surround Gate Junctionless Transistor than SiO₂ based device. From the analysis, it is found that HfO₂ will be a better alternative for the future nanoscale device.     

Wet thermal annealing effect on TaN/HfO2/Ge metal-oxide-semiconductor capacitors with and without a GeO2 passivation layer

Wet thermal annealing effects on the properties of TaN/HfO2/Ge metal-oxide-semiconductor(MOS) structures with and without a GeO2 passivation layer are investigated.The physical and the electrical properties are characterized by X-ray photoemission spectroscopy,high-resolution transmission electron microscopy,capacitance-voltage(C-V) and current-voltage characteristics.It is demonstrated that wet thermal annealing at relatively higher temperature such as 550℃ can lead to Ge incorporation in HfO2 and the partial crystallization of HfO2,which should be responsible for the serious degradation of the electrical characteristics of the TaN/HfO2/Ge MOS capacitors.However,wet thermal annealing at 400℃ can decrease the GeO x interlayer thickness at the HfO2/Ge interface,resulting in a significant reduction of the interface states and a smaller effective oxide thickness,along with the introduction of a positive charge in the dielectrics due to the hydrolyzable property of GeO x in the wet ambient.The pre-growth of a thin GeO2 passivation layer can effectively suppress the interface states and improve the C-V characteristics for the as-prepared HfO2 gated Ge MOS capacitors,but it also dissembles the benefits of wet thermal annealing to a certain extent.     

Chemical characterization by XPS of Cu/Ge ohmic contacts to n-GaAs

Chemical composition of Cu/Ge layers deposited on a 1 μm thick n-type GaAs epitaxial layer (doped with Te to a concentration of 5 × 10¹⁸ cm⁻³) and its interface were examined ex situ by XPS combined with Ar⁺ sputtering. These measurements indicate a diffusion of Cu and Ge from the Cu/Ge layer towards GaAs and, also, an out-diffusion of Ga and As from the GaAs layer to the metallic films. The Auger parameter corrected Auger spectra and XPS spectra show only Cu and Ge metals in the in the Cu/Ge layer and in the interface.     

Oxidation mechanism of hydrogen-terminated Ge(1 0 0) surface

Control of the surface chemistry to prepare a robust termination on the Ge surface is crucial for the development of high-end Ge devices. In this study, oxidation of a H-terminated Ge surface was studied in air ambient and H₂O using a multiple internal reflection Fourier transform infrared spectroscopy (MIR FT-IR) technique. Ge surface treated in less diluted HF exhibited a stronger Ge-H peak intensity, and the surface was easily oxidized in the air ambient. Therefore, it is believed that the treatment of the Ge surface in highly diluted HF solution has an advantage in suppressing the oxidation of Ge in the air ambient. For the oxidation of Ge(1 0 0) surface in air ambient, the Ge surface is attacked by oxidizing agents to break Ge-H and Ge-Ge bonds, and the transition GeO_x layer is first formed, followed by a layer-by-layer GeO₂ formation with the increase in exposure time. When the H-terminated Ge surface was treated in H₂O, GeO_x was mainly formed, the thickness of the oxide layer was not changed with an increase in treatment time, and the Ge surface was maintained in a suboxide state, which exhibits a different oxidation mechanism from that in air ambient.     

Surface chemistry of Fe2O3 nanoparticles on ultrathin oxide layers on Si and Ge

In this paper, we report on a comparative study of the effect of Fe₂O₃ nanoparticles (NP), introduced onto a thin oxide layer formed on silicon and germanium surfaces, on the thermal decomposition pathway of the individual oxide layers. On both the surfaces, NP of Fe₂O₃ undergo a reduction reaction through a bonding partner change reaction, where the oxygen atoms change from Fe to Si or Ge. On both the surfaces, annealing results in the conversion of the suboxide-like species to dioxide-like species (SiO_x to SiO₂ and GeO_x to GeO₂ respectively for Si and Ge surfaces), until the oxide layer decomposes following the desorption of the respective monoxide species (SiO and GeO). Both the Si and Ge corelevels show a larger chemical shift (4.1 and 3.51 eV in Si 2p and Ge 3d corelevels, respectively) for the as-prepared oxide samples with the NP, at room temperature compared to that without the NP (3.7 and 3.4 eV), indicating a catalytic enhancement of the dioxide formation. Selective formation of silicon oxides leads to encapsulation of the nanoparticles and acts like a protective layer, preventing the oxidation of Fe.     

Synthesis,characterization and radiation damage studies of high-k dielectric (HfO2) films for MOS device applications

The current trend in miniaturization of metal oxide semiconductor devices needs high-k dielectric materials as gate dielectrics. Among all the high-k dielectric materials, HfO₂ enticed the most attention, and it has already been introduced as a new gate dielectric by the semiconductor industry. High dielectric constant (HfO₂) films (10?nm) were deposited on Si substrates using the e-beam evaporation technique. These samples were characterized by various structural and electrical characterization techniques. Rutherford backscattering spectrometry, X-ray reflectivity, and energy-dispersive X-ray analysis measurements were performed to determine the thickness and stoichiometry of these films. The results obtained from various measurements are found to be consistent with each other. These samples were further characterized by I–V (leakage current) and C–V measurements after depositing suitable metal contacts. A significant decrease in the leakage current and the corresponding increase in device capacitance are observed when these samples were annealed in oxygen atmosphere. Furthermore, we have studied the influence of gamma irradiation on the electrical properties of these films as a function of the irradiation dose. The observed increase in the leakage current accompanied by changes in various other parameters, such as accumulation capacitance, inversion capacitance, flat band voltage, mid-gap voltage, etc., indicates the presence of various types of defects in irradiated samples.