Amorphous IZO TTFTs with saturation mobilities exceeding 100 cm2/Vs

In this paper we demonstrate the use of amorphous binary In₂O₃–ZnO oxides simultaneously as active channel layer and as source/drain regions in transparent thin film transistor (TTFT), processed at room temperature by rf sputtering. The TTFTs operate in the enhancement mode and their performances are thickness dependent. The best TTFTs exhibit saturation mobilities higher than 10² cm²/Vs, threshold voltages lower than 6 V, gate voltage swing of 0.8 V/dec and an on/off current ratio of 10⁷. This mobility is at least two orders of magnitude higher than that of conventional amorphous silicon TFTs and comparable to or even better than other polycrystalline semiconductors. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

High performance Zn–Sn–O thin film transistors with Cu source/drain electrode

Zn–Sn–O (ZTO) thin film transistors (TFTs) were fabricated with a Cu source/drain electrode. Although a reasonably high mobility (μ_FE) of 13.2 cm²/Vs was obtained for the ZTO TFTs, the subthreshold gate swing (SS) and threshold voltage (V_th) of 1.1 V/decade and 9.1 V, respectively, were inferior. However, ZTO TFTs with Ta film inserted as a diffusion barrier, exhibited improved SS and V_th values of 0.48 V/decade and 3.0 V, respectively as well as a high μ_FE value of 18.7 cm²/Vs. The improvement in the Ta‐inserted device was attributed to the suppression of Cu lateral diffusion into the ZTO channel region. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Highly stable amorphous indium‐zinc‐oxide thin‐film transistors with back‐channel wet‐etch process

The stabilities of amorphous indium‐zinc‐oxide (IZO) thin film transistors (TFTs) with back‐channel‐etch (BCE) structure are investigated. A molybdenum (Mo) source/drain electrode was deposited on an IZO layer and patterned by hydrogen peroxide (H₂O₂)‐based etchants. Then, after etching the Mo layer, SF₆ plasma with direct plasma mode was employed and optimized to improve the bias stress stability. Scanning electron microscopy and X‐ray photoelectron spectroscopic analysis revealed that the etching residues were removed efficiently by the plasma treatment. The modified BCE‐ TFTs showed only threshold voltage shifts of 0.25 V and –0.20 V under positive/negative bias thermal stress (P/NBTS, V_GS = ±30 V, V_DS = 0 V and T = 60 °C) after 12 hours, respectively. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Selective floating gate non‐volatile paper memory transistor

Here we report the performance of a selective floating gate (V_GS) n‐type non‐volatile memory paper field‐effect transistor. The paper dielectric exhibits a spontaneous polarization of about 1 mCm^–2 and GIZO and IZO amorphous oxides are used respectively as the channel and the gate layers. The drain and source regions are based in continuous conductive thin films that promote the integration of fibres coated with the active semiconductor. The floating memory transistor writes, reads and erases the stored information with retention times above 14500 h, and is selective (for V_GS > 5 ± 0.1 V). That is, to erase stored information a symmetric pulse to the one used to write must be utilized, allowing to store in the same space different information. (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

High‐performance In–Zn–O thin‐film transistors with a soluble processed ZrO2 gate insulator

Spin‐coated zirconium oxide films were used as a gate dielectric for low‐voltage, high performance indium zinc oxide (IZO) thin‐film transistors (TFTs). The ZrO₂ films annealed at 400 °C showed a low gate leakage current density of 2 × 10^–8 A/cm² at an electric field of 2 MV/cm. This was attributed to the low impurity content and high crystalline quality. Therefore, the IZO TFTs with a soluble ZrO₂ gate insulator exhibited a high field effect mobility of 23.4 cm²/V s, excellent subthreshold gate swing of 70 mV/decade and a reasonable I_on/off ratio of ～10⁶. These TFTs operated at low voltages (～3.0 V) and showed high drain current drive capability, enabling oxide TFTs with a soluble processed high‐k dielectric for use in backplane electronics for low‐power mobile display applications. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Double‐layer channel structure based ZnO thin‐film transistor grown by atomic layer deposition

A double channel structure has been used by depositing a thin amorphous‐AlZnO (a‐AZO) layer grown by atomic layer deposition between a ZnO channel and a gate dielectric to enhance the electrical stability. The effect of the a‐AZO layer on the electrical stability of a‐AZO/ZnO thin‐film transistors (TFTs) has been investigated under positive gate bias and temperature stress test. The use of the a‐AZO layer with 5 nm thickness resulted in enhanced subthreshold swing and decreased V_th shift under positive gate bias/temperature stress. In addition, the falling rate of the oxide TFT using a‐AZO/ ZnO double channel had a larger value (0.35 eV/V) than that of pure ZnO TFT (0.24 eV/V). These results suggest that the interface trap density between dielectric and channel was reduced by inserting a‐AZO layer at the interface between the channel and the gate insulator, compared with pure ZnO channel. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

High vertical breakdown strength in with low specific on‐resistance AlGaN/AlN/GaN HEMTs on silicon

Off‐state and vertical breakdown characteristics of AlGaN/AlN/GaN high‐electron‐mobility transistors (HEMTs) on high‐resistivity (HR)‐Si substrate were investigated and analysed. Three‐terminal off‐state breakdown (BV_gd) was measured as a function of gate–drain spacing (L_gd). The saturation of BV_gd with L_gd is because of increased gate leakage current. HEMTs with L_gd = 6 µm exhibited a specific on‐resistance R_DS[ON] of 0.45 mΩ cm². The figure of merit (FOM = BV_gd²/R_DS[ON]) is as high as 2.0 × 10⁸ V² Ω^–1 cm^–2, the highest among the reported values for GaN HEMTs on Si substrate. A vertical breakdown of ～1000 V was observed on 1.2 µm thick buffer GaN/AlN grown on Si substrate. The occurrence of high breakdown voltage is due to the high quality of GaN/AlN buffer layers on Si substrate with reduced threading dislocations which has been confirmed by transmission electron microscopy (TEM). This indicates that the AlGaN/AlN/GaN HEMT with 1.2 µm thick GaN/AlN buffer on Si substrate is promising candidate for high‐power and high‐speed switching device applications. (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

High‐mobility flexible thin‐film transistors with a low‐temperature zirconium‐doped indium oxide channel layer

Thin film transistors (TFTs) with zirconium‐doped indium oxide (ZrInO) channel layer were successfully fabricated on a flexible PEN substrate with process temperature of only 150 °C. The flexible ZrInO TFT exhibited excellent electrical performance with a saturation mobility of as high as 22.6 cm² V^–1 s^–1, a sub‐threshold swing of 0.39 V/decade and an on/off current ratio of 2.5 × 10⁷. The threshold voltage shifts were 1.89 V and ?1.56 V for the unpassivated flexible ZrInO TFT under positive and negative gate bias stress, respectively. In addition, the flexible ZrInO TFT was able to maintain the relatively stable performance at bending curvatures larger than 20 mm, but the off current increased apparently after bent at 10 mm. Detailed studies showed that Zr had an effect of suppress the free carrier generation without seriously distorting the In₂O₃ lattice. (© 2016 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

Effect of antimony doping on the low‐temperature performance of solution‐processed indium oxide thin film transistors

The effects of antimony (Sb) doping on solution‐processed indium oxide (InO_x) thin film transistors (TFTs) were examined. The Sb‐doped InSbO TFT exhibited a high mobility, low gate swing, threshold voltage, and high I_ON/OFF ratio of 4.6 cm²/V s, 0.29 V/decade, 1.9 V, and 3 × 10⁷, respectively. The gate bias and photobias stability of the InSbO TFTs were also improved by Sb doping compared to those of InO_x TFTs. This improvement was attributed to the reduction of oxygen‐related defects and/or the existence of the lone‐pair s‐electron of Sb³⁺ in amorphous InSbO films. (© 2014 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

The role of metal contacts in the stability of n-type organic field effect transistors

We are presenting a long-time bias stress stability of C₆₀-based n-type organic field effect transistors (OFETs), in bottom gate, top contacts configuration, with aluminium (Al), silver (Ag) and gold (Au) source–drain contacts. The results clearly shows that the bias stress effects in C₆₀-based n-type OFETs is similar to p-type OFETs and it can be reduced by using an appropriate metal for the source–drain contacts. During the bias stress time, the threshold voltage shift and an increase in the contacts resistance have also been measured. On the basis of the stability of the device parameters, it is proposed that the Al source–drain contact-based devices gives better stability as compared to the devices with Ag and Au source–drain contacts. Our results show that the bias stress-induced threshold voltage shift is due to the trapping of charges in the channel region and in the vicinity of the source–drain contacts.     

The effect of barrier strain on the reliability of Inx Al1–xN/AlN/GaN heterostructure field‐effect transistors

We report on the reliability of In_x Al_1–xN/AlN/GaN‐based heterostructure field‐effect transistors (HFETs) fabricated on five different wafers with varying indium compositions (0.12 ≤ x ≤ 0.20) encompassing the tensile/compressive strain fields. All of the tested devices underwent high field on‐state stress at 20 V DC drain bias and zero gate bias for five hours. We monitored the drain current and low‐frequency noise (LFN) a priori and a posteriori the stress treatment to quantify device degradation. HFETs suffering tensile strain showed remarkably large degradation which manifested itself with up to 25 dB increase in noise power and up to 72% loss of drain current after stress. On the other hand, devices fabricated on compressively strained structures remained intact after stress, but they had about 30 dB higher pre‐stress noise‐power levels and about 50% lower drain‐current densities to begin with. The results show that the nearly lattice‐matched In_0.17Al_0.83N barrier exhibited very low degradation along with current density remaining high compared with the devices having barriers with lower or higher indium content. Our results suggest that the nearly‐lattice‐matched InAlN can be a good candidate for devices due to its relatively better reliability while maintaining a high current density. (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Effect of temperature–bias annealing on the hysteresis and subthreshold behavior of multilayer MoS2 transistors

The transfer characteristics (I_D–V_G) of multilayers MoS₂ transistors with a SiO₂/Si backgate and Ni source/drain contacts have been measured on as‐prepared devices and after annealing at different temperatures (T_ann from 150 °C to 200 °C) under a positive bias ramp (V_G from 0 V to +20 V). Larger T_ann resulted in a reduced hysteresis of the I_D–V_G curves (from ～11 V in the as‐prepared sample to ～2.5 V after T_ann at 200 °C). The field effect mobility (～30 cm² V^–1 s^–1) remained almost unchanged after the annealing. On the contrary, the subthreshold characteristics changed from the common n‐type behaviour in the as‐prepared device to the appearance of a low current hole inversion branch after annealing. This latter effect indicates a modification of the Ni/MoS₂ contact that can be explained by the formation of a low density of regions with reduced Schottky barrier height (SBH) for holes embedded in a background with low SBH for electrons. Furthermore, a temperature dependent analysis of the subthreshold characteristics revealed a reduction of the interface traps density from ～9 × 10¹¹ eV^–1cm^–2in the as‐prepared device to ～2 × 10¹¹ eV^–1cm^–2after the 200 °C temperature–bias annealing, which is consistent with the observed hysteresis reduction.

Schematic representation of a back‐gated multilayer MoS₂ field effect transistor (left) and transfer characteristics (right) measured at 25 °C on an as‐prepared device and after the temperature–bias annealing at 200 °C under a positive gate bias ramp from 0 V to +20 V.     

Investigation of cation–anion interaction in 1‐(2‐hydroxyethyl)‐3‐methylimidazolium‐based ion pairs by density functional theory calculations and experiments

Gas‐phase structure, hydrogen bonding, and cation–anion interactions of a series of 1‐(2‐hydroxyethyl)‐3‐methylimidazolium ([HOEMIm]⁺)‐based ionic liquids (hereafter called hydroxyl ILs) with different anions (X = [NTf₂]^–, [PF₆]^–, [ClO₄]^–, [BF₄]^–, [DCA]^–, [NO₃]^–, [AC]^– and [Cl]^–), as well as 1‐ethyl‐3‐methylimizolium ([EMIm]⁺)‐based ionic liquids (hereafter called nonhydroxyl ILs), were investigated by density functional theory calculations and experiments. Electrostatic potential surfaces and optimized structures of isolated ions, and ion pairs of all ILs have been obtained through calculations at the Becke, three‐parameter, Lee–Yang–Parr/6‐31 + G(d,p) level and their hydrogen bonding behavior was further studied by the polarity and Kamlet–Taft Parameters, and ¹H‐NMR analysis. In [EMIm]⁺‐based nonhydroxyl ILs, hydrogen bonding preferred to be formed between anions and C2–H on the imidazolium ring, while in [HOEMIm]⁺‐based hydroxyl ILs, it was replaced by a much stronger one that preferably formed between anions and OH. The O–H···X hydrogen bonding is much more anion‐dependent than the C2–H···X, and it is weakened when the anion is changed from [AC]^– to [NTf₂]^–. The different interaction between [HOEMIm]⁺ and variable anion involving O–H···X hydrogen bonding resulted in significant effect on their bulk phase properties such as ¹H‐NMR shift, polarity and hydrogen‐bond donor ability (acidity, α). Copyright © 2011 John Wiley & Sons, Ltd.     

High-performance Zinc-Tin-Oxide thin film transistors based on environment friendly solution process

Zinc-Tin-Oxide (ZTO) thin films were fabricated using a simple and eco-friendly sol-gel method and their application in thin film transistors (TFTs) was investigated. Annealing temperature has a crucial influence on the structure and electrical properties of sol-gel ZTO thin films. The ZTO thin films annealed at 300–600?°C revealed smooth and uniform surfaces with amorphous state, in addition, a high optical transparency over 90% of the ZTO films in the visible range was obtained. The electrical performance of ZTO TFTs showed obvious dependence on annealing temperature. The ZTO TFTs annealed at 500?°C showed a high carrier mobility of 5.9?cm²/V, high on/off current ratio (I_on/off) of 10⁶-10⁷, and threshold voltage (V_th) of 1.03?V. To demonstrate the application of sol-gel ZTO films in low-power display fields, we also fabricated ZTO TFTs with a solution-processed high-permittivity (high-k) ZrTiO_x dielectric layer. The ZTO/ZrTiO_x TFTs showed high mobility of 17.9?cm²/V and I_on/off of 10⁵-10⁶?at a low operation voltage of 3?V, indicating that Indium-free ZTO thin films would be potential candidates for low cost, high performance oxide TFT devices.     

Drop‐cast and dye‐sensitized ZnO nanorod‐based visible‐light photodetectors

We report the facile fabrication of metal–semiconductor–metal (MSM) photodetectors with dye‐sensitized ZnO nanorods (NRs) operating at wavelengths of ～405–638 nm by a simple drop casting method. The ZnO NRs were synthesized by the hydrothermal synthesis method at 75 °C. The droplet of ethanol solution containing ZnO NRs was dropped between two metal electrodes and dried at 65 °C, which allows the ZnO NRs to be adhered and contacted to both metal electrodes. When a violet light of 405 nm was illuminated into the MSM ZnO NRs‐based photodetector, the photocurrent gain was obtained as ～3.9 × 10³ at the applied bias voltage of 5 V. By increasing the bias voltage from 10 V to 15 V, the device exhibited good recovery performance with a largely reduced reset time from 85.68 s to 2.47 s and an increased on–off ratio from 17.9 to 77.4. To extend the photodetection range towards the long visible spectral region, the ZnO NRs were sensitized by the N719 dye and then drop‐cast. The dye‐sensitized ZnO NRs‐based photodetector also exhibited good photocurrent switching under 638 nm of light illumination. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Identification of grain boundaries as degradation site in n‐channel organic field‐effect transistors determined via conductive atomic force microscopy

One important figure of merit for the commercial usability of organic transistors (OFETs) is their electrical stability. With the aim of identifying the microscopic location of degradation sites within a transistor channel, we have investigated the bias stress stability of OFETs by electrical measurements as well as by conductive atomic force microscopy. Air‐stable n‐channel FETs based on a N,N′‐bis(2‐ethylhexyl)‐1,7(1,6)‐dicyano‐perylene[3,4:9,10]bis (dicarboximide) were fabricated to understand the relation between the thin‐film morphology, the substrate temperature during the vacuum de position with the aim to fabricate transistors with a mobility not dominated by interface traps. The devices showed a maximum carrier mobility of (0.12 ± 0.01) cm²/V s and an on/off ratio up to 10⁷. The electrical performance as well as the bias stress behavior of the semiconductor thin‐films is significantly influenced by grain boundaries. For example, the grain boundary resistance was found to increase upon electrical stress by more than 150% (from 2 ± 0.2 GΩ to 5 ± 1.5 GΩ), while the resistance within the grains remains unchanged. (© 2016 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

Calibrated numerical model of a GaInP–GaAs dual‐junction solar cell

In this letter a calibrated numerical model of a III–V dual‐junction solar cell including tunnel diode and Bragg reflector is presented. The quantum efficiencies of the subcells are computed by using the principle of current‐limitation in monolithic multi‐junction solar cells. A special procedure with bias‐illumination and bias‐voltage was implemented. Numerical simulations are used to study the influence of the top cell thickness on the cells' quantum efficiency and on the current‐matching condition. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Formation of three‐dimensional GaAs microstructures by combination of wet and metal‐assisted chemical etching

Previously, plasma‐enhanced dry etching has been used to generate three‐dimensional GaAs semiconductor structures, however, dry etching induces surface damages that degrade optical properties. Here, we demonstrate the fabrication method forming various types of GaAs microstructures through the combination etching process using the wet‐chemical solution. In this method, a gold (Au)‐pattern is employed as an etching mask to facilitate not only the typical wet etching but also the metal‐assisted chemical etching (MacEtch). High‐aspect‐ratio, tapered GaAs micropillars are produced by using [HF]:[H₂O₂]:[EtOH] as an etching solution, and their taper angle can be tuned by changing the molar ratio of the etching solution. In addition, GaAs microholes are formed when UV light is illuminated during the etching process. Since the wet etching process is free of the surface damage compared to the dry etching process, the GaAs microstructures demonstrated to be well formed here are promising for the applications of III–V optoelectronic devices such as solar cells, laser diodes, and photonic crystal devices. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Junctionless nanowire transistor fabricated with high mobility Ge channel

The junctionless nanowire metal–oxide–semiconductor field‐effect transistor (JNT) has recently been proposed as an alternative device for sub‐20‐nm nodes. The JNT architecture eliminates the need for forming PN junctions, resulting in simple processing and competitive electrical characteristics. In order to further boost the drive current, alternative channel materials such as III–V and Ge, have been proposed. In this Letter, JNTs with Ge channels have been fabricated by a CMOS‐compatible top–down process. The transistors exhibit the lowest subthreshold slope to date for JNT with Ge channels. The devices with a gate length of 3 μm exhibit a subthreshold slope (SS) of 216 mV/dec with an I_ON/I_OFF current ratio of 1.2 × 10³ at V_D = –1 V and drain‐induced‐barrier lowering (DIBL) of 87 mV. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

基于氧化铟锡的无结低电压薄膜晶体管

在室温下制备了基于氧化铟锡(ITO)的底栅结构无结薄膜晶体管. 源漏电极和沟道层都是同样的ITO薄膜材料,没有形成传统的源极结和漏极结, 因而极大的简化了制备流程,降低了工艺成本.使用具有大电容的双电荷层SiO₂作为栅介质, 发现当ITO沟道层的厚度降到约20 nm时, 器件的栅极电压可以很好的调控源漏电流. 这些无结薄膜晶体管具有良好的器件性能: 低工作电压(1.5 V), 小亚阈值摆幅(0.13 V/dec)、 高迁移率(21.56 cm²/V·s)和大开关电流比(1.3× 10⁶). 这些器件即使直接在大气环境中放置4个月, 器件性能也没有明显恶化:亚阈值摆幅保持为0.13 V/dec,迁移率略微下降至18.99 cm²/V·s,开关电流比依然大于10⁶.这种工作电压低、工艺简单、 性能稳定的无结低电压薄膜晶体管非常有希望应用于低能耗便携式电子产品以及新型传感器领域.