The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-k gate dielectrics |
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| Authors: | Ma Fei Liu Hong-Xia Kuang Qian-Wei Fan Ji-Bin |
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| Affiliation: | Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Material and Devices, School of Microelectronics, Xidian University, Xi'an 710071, China |
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| Abstract: | The fringing-induced barrier lowering (FIBL) effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator. An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect. The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance. Based on equivalent capacitance theory, the influences of channel length, junction depth, gate/lightly doped drain (LDD) overlap length, spacer material and spacer width on FIBL is thoroughly investigated. A stack gate dielectric is presented to suppress the FIBL effect. |
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| Keywords: | high-k gate dielectric fringing-induced barrier lowering stack gate dielectric MOSFET |
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