A 9‐Bit 80‐MS/s CMOS Pipelined Folding A/D Converter with an Offset Canceling Technique

A 9‐bit 80‐MS/s CMOS pipelined folding analog‐to‐digital converter employing offset‐canceled preamplifiers and a subranging scheme is proposed to extend the resolution of a folding architecture. A fully differential dc‐decoupled structure achieves high linearity in circuit design. The measured differential nonlinearity and integral nonlinearity of the prototype are ×0.6 LSB and ×1.6 LSB, respectively.