A scaled, high-performance (4.5 fJ) bipolar device in a 0.35 μmhigh-density BiCMOS SRAM technology |
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Authors: | Taft R.C. Hayden J.D. |
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Affiliation: | East Coast Labs. Inc., Salem, NH; |
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Abstract: | We present the performance improvements obtained both by scaling the Selectively Compensated Collector (SCC) BJT and by using a modified Current-Mode Logic (CML) gate configuration. Scaling the perimeter parameter by using the (tighter) bitcell design rules results in a ~30% reduction in parasitic capacitances, and a 23% lower power-delay product; reducing it from 48 fJ to 37 fJ. The greatest return comes from using a modified CML gate, which has an n-MOS current source. At a supply voltage of 1.1 V, and at 40 μA switching current, the minimum power-delay product of this CML gate is a silicon-substrate bipolar record 4.5 fJ |
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