Hardware implementation of pseudo-random number generators based on chaotic maps

We show the usefulness of bifurcation diagrams to implement a pseudo-random number generator (PRNG) based on chaotic maps. We provide details on the selection of the best parameter values to obtain high entropy and positive Lyapunov exponent from the bifurcation diagram of four chaotic maps, namely: Bernoulli shift map, tent, zigzag, and Borujeni maps. The binary sequences obtained from these maps are analyzed to implement a PRNG both in software and in hardware. The software implementation is realized using 32 and 64 bits microprocessor architectures, and with floating point and fixed point computer arithmetic. The hardware implementation is done by using a field-programmable gate array (FPGA) architecture. We developed a serial communication interface between the PRNG on the FPGA and a personal computer to obtain the generated sequences. We validate the randomness of the generated binary sequences with the NIST test suite 800-22-a both in floating point and fixed point arithmetic. At the end, we show that those chaotic maps are suitable to implement a PRNG but according to the hardware resources, the one based on the Bernoulli shift map is better. In addition, another advantage is that the required initial value for the sequences can be within the whole interval \(-1,1]\), including its bounds.