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| 65nm工艺下基于PCI Express2.0协议的物理编码子层设计 | |
| 引用本文： | 刘奇浩,翁惠辉,张锋,赵建中,吕俊盛,李优.65nm工艺下基于PCI Express2.0协议的物理编码子层设计[J].中国集成电路,2013,22(3):40-45. |
| 作者姓名： | 刘奇浩 翁惠辉 张锋 赵建中 吕俊盛 李优 |
| 作者单位： | 1. 长江大学电子信息学院,湖北荆州,34023;中国科学院微电子研究所,北京,100029 2. 长江大学电子信息学院,湖北荆州,34023 3. 中国科学院微电子研究所,北京,100029 |
| 基金项目： | 国家"八六三"计划项目 |
| 摘 要： | 设计了一种应用于PCIExpress2．0协议的物理编码子层，可以与物理媒介连接子层共同构成独立的物理层芯片。本文从面积与功耗方面对8b10b编解码的两种实现方法进行比较；并设计了复位控制器、头字符检测电路、时钟补偿弹性缓冲器、内建自测试等电路。全部电路在SMIC65nraCMOS工艺下综合，SS工艺角、工作频率500MHz条件下芯片面积为5500μmz，动态功耗为2．74mW。 |
| 关 键 词： | PEI Expres s2 0 物理编码子层 8b10b编解码 弹性缓冲器 |
An Efficient Physical Coding Sublayer for PCI Express2.0 in 65nm CMOS |
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| LIU Qi-hao , WENG Hui-hui , ZHANG Feng , ZHAO Jian-zhong , LV Jun-sheng , LI You.An Efficient Physical Coding Sublayer for PCI Express2.0 in 65nm CMOS[J].China Integrated Circuit,2013,22(3):40-45. | |
| Authors: | LIU Qi-hao WENG Hui-hui ZHANG Feng ZHAO Jian-zhong LV Jun-sheng LI You |
| Institution: | 2 (1.Institute of Electronic and Information, Yangtze University, Jingzhou 434020, China; 2.Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China) |
| Abstract: | An efficient Physical Coding Sublayer operating at 500MHz has been implemented based process for PCI Express 2.0, which was integrated into PHY with physical media attachment layer. on 65 nm CMOS Two methods of 8bl0b codec were compared in area and dynamic power consumption. A reset controller for initialization, elastic buffer for clock compensation and built-in-self-test circuit were employed. The circuit was synthesized at the speed of 500MHz in SS with an area of about 5500 μ m2 and the dynamic power consumption of 2.74 mW operating in FF. |
| Keywords: | PCI Express2 0 PCS 8bl0b elastic buffer BIST |
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