Junctionless nanowire transistor fabricated with high mobility Ge channel |
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| Authors: | Ran Yu Samaresh Das Richard G Hobbs Ian M Povey Nikolay Petkov Maryam Shayesteh Dan O'Connell Justin D Holmes Ray Duffy |
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| Institution: | 1. Tyndall National Institute, Lee Maltings, Dyke Parade, Ireland;2. Hitachi Cambridge Laboratory, Hitachi Europe Ltd., Cambridge CB3 0HE, UK;3. Research Laboratory of Electronics, Massachusetts Institute of Technology, Building 36 – Room 283, MA, USA;4. Materials Chemistry and Analysis Group, Department of Chemistry, University College Cork, Cork, Ireland |
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| Abstract: | The junctionless nanowire metal–oxide–semiconductor field‐effect transistor (JNT) has recently been proposed as an alternative device for sub‐20‐nm nodes. The JNT architecture eliminates the need for forming PN junctions, resulting in simple processing and competitive electrical characteristics. In order to further boost the drive current, alternative channel materials such as III–V and Ge, have been proposed. In this Letter, JNTs with Ge channels have been fabricated by a CMOS‐compatible top–down process. The transistors exhibit the lowest subthreshold slope to date for JNT with Ge channels. The devices with a gate length of 3 μm exhibit a subthreshold slope (SS) of 216 mV/dec with an ION/IOFF current ratio of 1.2 × 103 at VD = –1 V and drain‐induced‐barrier lowering (DIBL) of 87 mV. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim) |
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| Keywords: | germanium junctionless lithography high‐k |
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