| 高速Viterbi处理器—流水式块处理并行结构 |
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| 引用本文： | 宣建华,姚庆栋.高速Viterbi处理器—流水式块处理并行结构[J].通信学报,1995,16(1):94-100. |
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| 作者姓名： | 宣建华 姚庆栋 |
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| 作者单位： | 浙江大学，浙江大学 杭州 310008，杭州 310008 |
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| 摘 要： | 本文提出一种流水式块处理并行Ｖｉｔｅｒｂｉ处理器，可以得到ＬＭ倍增速（Ｍ为流水级数，Ｌ为块长度），为达到更高速的Ｖｉｔｅｒｂｉ处理器提供了新型的并行结构。它可用Ｓｙｓｔｏｌｉｅ阵列构成，因而适于ＶＬＳＩ实现。
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| 关 键 词： | Viterbi处理器 并行结构 流水处理 块处理 |
High Rate Viterbi Processor: A Parallel Pipelined Blocking Processing Architecture |
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| Xuan Jianhua Yao Qingdong.High Rate Viterbi Processor: A Parallel Pipelined Blocking Processing Architecture[J].Journal on Communications,1995,16(1):94-100. |
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| Authors: | Xuan Jianhua Yao Qingdong |
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| Abstract: | In this paper, a pipelined block processing Viterbi processor is described , which can provide a speedup by a factor of LM over conventional algorithm by using with a block size of L, and M pipeline stages inside the recursive loop of the block processing Viterbi processing. Also, Systolic array is suitable for this algorithm and hence for its VLSI implementation. |
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| Keywords: | Viterbi processor parallel architecture pipelining processing block processing |
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