A low subthreshold swing tunneling field effect transistor for next generation low power CMOS applications

We propose a low subthreshold swing transistor architecture called Negative Capacitance Single Gate Silicon-On-Insulator Tunneling Field Effect Transistor (NC-SG-SOI-TFET) and present an analytical model to characterize its performance. Electrostatic potential distribution and electric field intensity in the channel region are obtained by solving the Poisson equation, and the drain current is calculated using the band-to-band carrier generation rate. An additional layer of ferroelectric oxide is used to obtain the negative capacitance. Effect of ferroelectric oxide is incorporated using one-dimensional Landau formalism. Through two dimensional theoretical analysis, we show that the proposed device has superior performance over traditional TFETs in terms of subthreshold swing and short channel effects. For example, a subthreshold swing of 11.82 mV/decade and operating voltage of 0.65 V for a drain current of 10⁻⁸ A/µm have been obtained. The physics behind the improved performance is discussed based on the presented model. The analytical model would also be instrumental in designing and optimizing such devices avoiding complexities and cost of numerical models.