Sparse chip equalizer for DS-CDMA downlink receivers

We present a low complexity sparse chip equalization scheme for DS-CDMA downlink receivers in which only a small number of filter taps are selected to be non-zero, thereby reducing the computational complexity significantly. Low complexity algorithms for selecting the timings and complex amplitudes of the sparse equalizer taps are proposed. The excellent performance achieved by this scheme combined with its low complexity makes it an attractive choice for the DS-CDMA based cellular downlink receivers.