| 一种可重构处理器的设计 |
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| 引用本文： | 董培良,俞承芳.一种可重构处理器的设计[J].复旦学报(自然科学版),2004,43(1):45-49. |
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| 作者姓名： | 董培良 俞承芳 |
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| 作者单位： | 复旦大学,电子工程系,上海,200433;复旦大学,电子工程系,上海,200433 |
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| 摘 要： | 以主流FPGA为平台设计了一个可重构处理器．该处理器在与现有处理器内核全兼容的基础上，把指令总线和数据总线作为可重构部件的扩展接口，具有简单可靠的部件指令扩展规则、数据通讯方式和部件识别机制．重构操作的工作方式、数据保护机制也在设计中被充分考虑。
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| 关 键 词： | 可重构处理器 可重构系统 现场可编程门阵列 |
| 文章编号： | 0427-7104(2004)01-0045-05 |
Design of A Reconfigurable Processor |
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| DONG Pei-liang,YU Cheng-fang.Design of A Reconfigurable Processor[J].Journal of Fudan University(Natural Science),2004,43(1):45-49. |
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| Authors: | DONG Pei-liang YU Cheng-fang |
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| Abstract: | A reconfigurable processor is designed with the mainstream FPGA as its platform. This processor is fully compatible with the existing processor. The instruction bus and data bus are used as the extended interface for the reconfigurable modules. The rules instruction extension of reconfigurable modules, modes of data communication, and the mechanism of module identification of this processor are compact and reliable. Manipulation of reconfiguration and the mechanism of on-spot data protection are also carefully considered. |
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| Keywords: | reconfigurable processor reconfigurable system FPGA |
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