65nmSRAM两极多路选择器的设计

为提高SRAM的存取速度,节省芯片面积,抑制工艺波动的影响,在对SRAM多路选择架构研究基础上改进了一种应用于65 nm SRAM的多路选择架构,建立了此多路选择架构的小信号模型.采用蒙特卡罗仿真导出了位线传输管的最小尺寸限制.同时,提出一种简单的估算电路节点时间常数的方法,用于从理论上分析改进的两级架构相对于传统的一级架构的优势,即当两级架构的两级译码的特征数字相近时可取得最佳性能,且灵敏放大器的特征数字越大时两级架构的优势越明显.仿真验证的结果显示,在面积几乎不变、控制复杂性几乎不增加前提下,该两级架构最多可以使SRAM读取时间比传统一级结构减少33.6%.

Design of the two-tier MUX in 65 nm SRAM

In order to increase SRAM access speed,reduce chip area and suppress process fluctuations,an improved multiplexer（MUX） architecture applied to 65 nm SRAM was proposed based on the research of SRAM MUX architecture and its small signal model was built.Besides,the critical dimensions of transmission transistor were derived from Monte Carlo simulation.To demonstrate the superiority of the improved two-tier architecture to the conventional one-tier one,an easy method to estimates the time constant of electronic circuit nodes was introduced.Using the method,a useful conclusion was deduced that the proposed two-tier architecture could achieve the best performance when the characteristic numbers of the two-stage decoder are similar.In addition,the larger the characteristic number of sense amplifier（SA）,the better the two-tier architecture in comparison with one-tier one.Simulation results showed that the similar area and control complexity,the utilization of two-tier architecture could reduce to 33.6% of the read access time compared with the conventional one-tier one.