| Fast Fourier transform processor architecture |
| |
| 作者姓名： | ZHU Yubin and HOU Chaohuan |
| |
| 作者单位： | Institute of Acoustics. Academla Stnica，Beijing 100080 |
| |
| 摘 要： | This paper describes a VLSI architecture used for implementation offast Fourier transform,of which the computation cell(CC)implement the com-putation of 4-point DFT and multiplication of twiddle factors using radix-4pipeline computation method,and the address generator(AG)gives the ad-dresses of both transform data and twiddle factors simultaneously.In addition,this paper also presents the recursive and cascade circuit configurations usingthe CC,AG and BFP overflow preventing scheme.Up to 64K-point FFT canbe computed quickly and flexibly by using these two circuit configurations.
|
Fast Fourier transform processor architecture |
| |
| Authors: | ZHU Yubin and HOU Chaohuan |
| |
| Abstract: | This paper describes a VLSI architecture used for implementation of fast Fourier transform, of which the computation cell(CC) implement the computation of 4-point DFT and multiplication of twiddle factors using radix-4 pipeline computation method, and the address generator (AG) gives the addresses of both transform data and twiddle factors simultaneously. In addition, this paper also presents the recursive and cascade circuit configurations using the CC, AG and BFP overflow preventing scheme. Up to 64K-point FFT can be computed quickly and flexibly by using these two circuit configurations. |
| |
| Keywords: | FFT BFP VLSI architecture |
| 本文献已被 CNKI 等数据库收录！ |
