ESD protection for the tolerant I/O circuits using PESD implantation |
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| Institution: | 1. Equipe Synthèse Propriétés et Modélisation des Matériaux, Institut de Chimie Moléculaire et des Matériaux d′Orsay, Université Paris-Sud, Université Paris-Saclay, 91405 Orsay, France;2. Laboratoire Léon Brillouin, CEA, CNRS, Université Paris-Saclay, F-91191 Gif sur Yvette, France;3. Institut Nanosciences et Cryogénie (INAC)–Service de Physique Statistique Magnétisme et Supraconductivité (SPMS), CEA and Université Joseph Fourier, F-38000 Grenoble, France;1. Wolfson Centre for Magnetics, School of Engineering, Cardiff University, Cardiff CF24 3AA, UK;2. Institute of Physics, Polish Academy of Science, Warsaw 02-668, Poland;3. Department of Electrical and Computer Engineering, Iowa State University, Ames IA 50011, USA;4. Ames Laboratory, US Department of Energy, Ames IA 50011, USA;5. Global Research, GE India Technology Center, Whitefield, Bangalore KA 560066, India;1. School of Physics and Astronomy, Schuster Building, The University of Manchester, Manchester M13 9PL, UK;2. School of Physics and Astronomy, University of Minnesota, 116 Church Street SE, Minneapolis, MN 55455, USA;1. Institut Jean Lamour, UMR 7198 CNRS-Université Lorraine, Parc de Saurupt, 54011 Nancy, France;2. CRISMAT, UMR 6508 CNRS/ENSICAEN, LUSAC, Université de Caen Basse-Normandie, 6 Bd Maréchal Juin, 14050 CAEN Cedex 04, France;3. Institut Laue-Langevin (ILL), 6 rue J. Horowitz, BP 156-38042 Grenoble, Cedex 09, France |
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| Abstract: | In this paper, we propose an electrostatic discharge (ESD) solution with cascode structure for deep-submicron integrated circuits technology to enhance its ESD robustness. Using the added boron implantation (we call “PESD” implantation here) at the drain side of the stacked n-type metal-oxide semiconductor (NMOS), the long-base parasitic NPN (i.e., emitter, base and collector in the bipolar transistor are n-type, p-type, and n-type, respectively) bipolar transistor in the cascode NMOS structure can be easily triggered by the Zener breakdown mechanism at the drain side under ESD stress conditions. Based on UMC 0.25 μm process, this method provides a significant improvement in the cascode ESD performance. |
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