VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC |
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Authors: | Yi-Hau Chen Tung-Chien Chen Shao-Yi Chien Yu-Wen Huang Liang-Gee Chen |
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Institution: | (1) DSP/IC Design Lab., Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, 1, Sec. 4, Roosevelt Rd., Taipei, 10617, Taiwan |
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Abstract: | The H.264/AVC Fractional Motion Estimation (FME) with rate-distortion constrained mode decision can improve the rate-distortion
efficiency by 2–6 dB in peak signal-to-noise ratio. However, it comes with considerable computation complexity. Acceleration
by dedicated hardware is a must for real-time applications. The main difficulty for FME hardware implementation is parallel
processing under the constraint of the sequential flow and data dependency. We analyze seven inter-correlative loops extracted
from FME procedure and provide decomposing methodologies to obtain efficient projection in hardware implementation. Two techniques,
4×4 block decomposition and efficiently vertical scheduling, are proposed to reuse data among the variable block size and
to improve the hardware utilization. Besides, advanced architectures are designed to efficiently integrate the 6-taps 2D finite
impulse response, residue generation, and 4×4 Hadamard transform into a fully pipelined architecture. This design is finally
implemented and integrated into an H.264/AVC single chip encoder that supports realtime encoding of 720×480 30fps video with
four reference frames at 81 MHz operation frequency with 405 K logic gates (41.9% area of the encoder).
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Keywords: | H 264/AVC Motion estimation VLSI architecture Video coding |
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