Optimal gate sizing using a self-tuning multi-objective framework

In this paper, we present a self-tuning multi-objective framework for geometric programming that provides a fine trade-off between the competing objectives. The significance of this framework is that the designer does not need to perform any tuning of weights of objectives. The proposed framework is applied to gate sizing and clock network buffer sizing problems. In gate sizing application, power consumption is reduced on average by 86% while delay sees only an increase of 34 ns. In clock network butter sizing application, our framework results in a significant reduction in power, 57%, and an improvement of 31 ps in skew.