应用于无线通信领域4.1 GHz锁相环的设计

在分析锁相环线性模型的基础上，分析了影响锁相环系统的各种因素，采用相应的优化方法设计了一款4.1GHz LC锁相环。详细介绍了该锁相环中各模块电路（包括Lc型压控振荡器，高速分频器，数字分频器，鉴频／鉴相器，电荷泵以及无源滤波器等）的设计，并且给出了仿真结果。其中高速分频器采用TSPC逻辑电路，速度快功耗低。该锁相环采用SMIC 0.18um CMOS工艺设计，当VCO工作在4．1GHz时，在频偏为600kHz的相位噪声为-110dBc。

Design of 4.1 GHz Phase-Locked Loop for Wireless Applications

A 4. 1 GHz phase??locked loop ( PLL) is desig ned in a 0. 18 ??m 1. 8 V 1P6M CMOS techno logy. The PLL consists o f a LC??tank circuit , charg e pump, f requency/ phase detecto r, f requency div ider , pres?? caler and a passive loop filter. T he prescaler is in T SPC( T rue??Single??Phase??Clocking) logic. T he use of dy?? namic lo gic is not only possible up to 5 GHz, but also ext remely ef fect ive in reducing the synthesizer pow er dissipat ion. T he PLL intended for a w ireless receiver. T he phase noise is low er than - 110 dBc@ 600 kHz w hen the VCO runs at 4. 1 GHz.