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基于定向故障注入的SRAM型FPGA单粒子翻转效应评估方法
引用本文:卢凌云,徐宇,李悦,李天文,蔡刚,杨海钢.基于定向故障注入的SRAM型FPGA单粒子翻转效应评估方法[J].微电子学,2017,47(1):135-140.
作者姓名:卢凌云  徐宇  李悦  李天文  蔡刚  杨海钢
作者单位:中国科学院电子学研究所, 北京 100190;中国科学院大学, 北京 100049,中国科学院电子学研究所, 北京 100190;中国科学院大学, 北京 100049,中国科学院电子学研究所, 北京 100190;中国科学院大学, 北京 100049,中国科学院电子学研究所, 北京 100190,中国科学院电子学研究所, 北京 100190,中国科学院电子学研究所, 北京 100190
基金项目:国家自然科学基金资助项目(61474120,61271149)
摘    要:介绍了一种基于定向故障注入的SRAM型FPGA单粒子翻转效应评估方法。借助XDL工具,该方法解析了Virtex-4 SX55型FPGA的帧地址与物理资源之间的对应关系;将电路网表中的资源按模块分组,利用部分重构技术分别对电路整体及各分组相关的配置帧进行随机故障注入,以评估电路整体及其子模块的抗单粒子翻转能力;按模块分组对电路分别进行部分三模冗余(TMR)加固和故障注入实验,以比较不同加固方案的效果。实验结果表明:电路的抗单粒子翻转能力与其功能和占用的资源有关;在FPGA资源不足以支持完全TMR的情况下,该方法可以帮助设计者找到关键模块并进行有效的电路加固。

关 键 词:SRAM型FPGA    单粒子翻转效应    故障注入    部分三模冗余
收稿时间:2016/2/3 0:00:00

Evaluation of Single Event Upset Effects in SRAM-Based FPGA Using Module-Oriented Fault Injection Techniques
LU Lingyun,XU Yu,LI Yue,LI Tianwen,CAI Gang and YANG Haigang.Evaluation of Single Event Upset Effects in SRAM-Based FPGA Using Module-Oriented Fault Injection Techniques[J].Microelectronics,2017,47(1):135-140.
Authors:LU Lingyun  XU Yu  LI Yue  LI Tianwen  CAI Gang and YANG Haigang
Institution:Institute of Electronics, Chinese Academy of Sciences, Beijing 100190,P.R.China;University of Chinese Academy of Sciences, Beijing 100049, P.R.China,Institute of Electronics, Chinese Academy of Sciences, Beijing 100190,P.R.China;University of Chinese Academy of Sciences, Beijing 100049, P.R.China,Institute of Electronics, Chinese Academy of Sciences, Beijing 100190,P.R.China;University of Chinese Academy of Sciences, Beijing 100049, P.R.China,Institute of Electronics, Chinese Academy of Sciences, Beijing 100190,P.R.China,Institute of Electronics, Chinese Academy of Sciences, Beijing 100190,P.R.China and Institute of Electronics, Chinese Academy of Sciences, Beijing 100190,P.R.China
Abstract:An evaluation method for single event upset(SEU) effects in SRAM-based FPGA using module-oriented fault injection was presented. The relationship between Virtex-4 SX55 FPGA''s frame address and physical resources was analyzed with XDL tools. The resources in netlist were divided into groups according to module''s partition, and random faults were injected separately into configuration frames related to entire design or a group by partial reconfiguration techniques, so as to assess the anti-SEU capability of the whole circuit and its sub-modules. Partial triple module redundancy(TMR) on sub-modules in each group was hardened, and fault injection tests were conducted respectively to compare the effectiveness of different reinforcement schemes. The results showed that anti-SEU capability of a circuit was relevant to its function and corresponding resources. When FPGA resources were not sufficient for complete TMR, it could help designers find the key sub-modules, so as to harden the circuit effectively.
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