| 基于位并行DA结构的高速FIR滤波器 |
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| 引用本文： | 周云,冯全源.基于位并行DA结构的高速FIR滤波器[J].微电子学,2016,46(3):383-386, 392. |
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| 作者姓名： | 周云 冯全源 |
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| 作者单位： | 西南交通大学 微电子研究所, 成都 611756,西南交通大学 微电子研究所, 成都 611756 |
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| 基金项目： | 国家自然科学基金资助项目(61271090)；四川省科技支撑计划资助项目(2015GZ0103) |
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| 摘 要： | 针对目前利用FPGA实现基于分布式算法(DA)FIR滤波器的不足,以及为了实现高速FIR滤波器,提出了一种位并行分布式算法结构的解决方案。采用位并行分布式算法和流水线式并行加法器树,在Xilinx Virtex5系列FPGA上实现了高速FIR滤波器。该滤波器工程经ISE 12.3综合、布局布线后,利用Modelsim SE 6.5和Matlab联合仿真。仿真结果表明,该设计可以提高滤波器处理速度,32阶的滤波器最高时钟频率可达到399.624 MHz。对滤波器进行进一步优化,节约了硬件资源占用。
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| 关 键 词： | 分布式算法 FIR滤波器 FPGA 位并行结构 |
A High Speed FIR Filter Based on Bit-Parallel DA |
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| ZHOU Yun and FENG Quanyuan.A High Speed FIR Filter Based on Bit-Parallel DA[J].Microelectronics,2016,46(3):383-386, 392. |
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| Authors: | ZHOU Yun and FENG Quanyuan |
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| Institution: | Institute of Microelectronics, Southwest Jiaotong University, Chengdu 611756, P. R. China and Institute of Microelectronics, Southwest Jiaotong University, Chengdu 611756, P. R. China |
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| Abstract: | In view of the existing disadvantages of FPGA implementation for FIR filter based on distributed arithmetic (DA), a solution based on bit-parallel structure was proposed for high-speed FIR filter. A high-speed FIR filter was realized on a Xilinx Virtex5 series FPGA by utilizing the bit-parallel DA and pipelined parallel adder tree. The synthesization, placement and routing of the filter project were done by ISE 12.3, followed by simulation with Modelsim SE 6.5 and Matlab. Simulation results showed that the design was efficient, the processing speed was improved, and the maximum clock frequency of 32nd order filter reached 399.624 MHz. Finally, further optimization had been done, which resulted in savings of hardware resources. |
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| Keywords: | Distributed arithmetic FIR filter FPGA Bit-parallel architecture |
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