Electrical characterization of MOS memory devices containing metallic nanoparticles and a high-k control oxide layer

We study the electrical characteristics of a MOS structure in which Pt nanoparticles are embedded. This structure has a tunneling oxide of 3.5 nm in thickness (a SiO₂ thermal oxide layer) on top of a Si wafer, and a control oxide of 27 nm (HfO₂ layer deposited by electron gun evaporation). The nanoparticles are deposited on the SiO₂ layer with electron gun evaporation, at room temperature. The electrical study of the structures demonstrates that the “write” process is initiated at low electric fields. This indicates that this type of memory structure can be very promising for the fabrication of high speed MOSFET memory devices with low power consumption. Our charge retention measurements also show promising results.