| CMOS电路中抗Latch-up的保护环结构研究 |
| |
| 引用本文： | 唐晨,孙伟锋,陆生礼.CMOS电路中抗Latch-up的保护环结构研究[J].现代电子技术,2006,29(4):109-111. |
| |
| 作者姓名： | 唐晨 孙伟锋 陆生礼 |
| |
| 作者单位： | 东南大学,国家ASIC系统工程技术研究中心,江苏,南京,210096 |
| |
| 摘 要： | 闩锁是CMOS集成电路中的一种寄生效应,这种PNPN结构一旦被触发,从电源到地会产生大电流,导致整个芯片的失效。针对芯片在实际测试中发现的闩锁问题,介绍了闩锁的测试方法,并且利用软件Tsuprem4和Medici模拟整个失效过程,在对2类保护环(多子环/少子环)作用的分析,以及各种保护结构的模拟基础之上,通过对比触发电压和电流,得到一种最优的抗Latch up版图设计方法,通过进一步的流片、测试,解决了芯片中的闩锁失效问题,验证了这种结构的有效性。
|
| 关 键 词： | 寄生双极型晶体管 保护环 闩锁 CMOS集成电路 |
| 文章编号： | 1004-373X（2006）04-109-03 |
| 收稿时间： | 2005-09-16 |
| 修稿时间： | 2005年9月16日 |
Research on Latch-up Guard Ring Issues in CMOS Circuits |
| |
| TANG Chen,SUN Weifeng,LU Shengli.Research on Latch-up Guard Ring Issues in CMOS Circuits[J].Modern Electronic Technique,2006,29(4):109-111. |
| |
| Authors: | TANG Chen SUN Weifeng LU Shengli |
| |
| Institution: | National ASIC System Engineering Research Center, Sou thesst University, Nanjing, 210096, China |
| |
| Abstract: | Latch-up is a parasitic effect in CMOS circuits.Once the PN PN structure is triggered,there will be high current from VDD to GND,which makes the chip invalidation.To the problems during latch-up test,the test method is introduced and the failure process is simulated by Tsuprem4 and Medici.With the two guard rings are analyzed and several structures are simulated,an efficient way of layout design is obtained after triggering voltage and current are compared.The validity is proved by the test results. |
| |
| Keywords: | parasitical bipolar transistor guard ring latch up CMOS circuits |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
|
