| DVB-S信道内码解码器的FPGA实现 |
| |
| 引用本文： | 胡海宇,于鸿洋.DVB-S信道内码解码器的FPGA实现[J].中国有线电视,2006(Z3). |
| |
| 作者姓名： | 胡海宇 于鸿洋 |
| |
| 作者单位： | 电子科技大学，电子科技大学 四川 成都610054，四川 成都610054 |
| |
| 摘 要： | 采用基于软件流水线的回溯法实现维特比译码中的幸存路径管理,从而有效节省了资源消耗,并提高了译码速度；从DVB-S解码器的整体系统结构考虑,使用一种高效的同步头锁定及内码信息确定的方案。整个设计在Xilinx公司的XC2VP30上实现。
|
| 关 键 词： | 卫星数字视频广播 维持比译码 回溯法 同步锁定 |
A FPGA Implementation of Inner Decoder in DVB-S System |
| |
| HU Hai-yu YU Hong-yang.A FPGA Implementation of Inner Decoder in DVB-S System[J].China Cable Television,2006(Z3). |
| |
| Authors: | HU Hai-yu YU Hong-yang |
| |
| Abstract: | Using trace back algorithm based on software pipelining to implement the survivor path management of Viterbi decoder,resource consumption reduces and decoding speed increases.Considering the architecture of DVB-S decoder,an effective solution is performed to detect the sync-word byte and obtain inner code in- formation.The entire application is designed and synthesized on Xilinx's XC2VP30. |
| |
| Keywords: | viterbi decoder trace back synchronization detection |
| 本文献已被 CNKI 等数据库收录！ |
