FPGA硬核处理器系统加速数字电路功能验证的方法

为了缩短专用集成电路和片上系统的功能验证周期，该文提出FPGA硬核处理器系统加速数字电路功能验证的方法。所提方法综合软件仿真功能验证和现场可编程门阵列原型验证的优点，利用集成在片上系统现场可编程门阵列器件中的硬核处理器系统作为验证激励发生单元和功能验证覆盖率分析单元，解决了验证速度和灵活性不能统一的问题。与软件仿真验证相比，所提方法可以有效缩短数字电路的功能验证时间；在功能验证效率和验证知识产权可重用方面表现优于现有的FPGA原型验证技术。

Accelerating Functional Verification for Digital Circuit with FPGA Hard Processor System

In order to reduce the functional verification cycle of application-specific integrated circuits and on-chip system, a method for accelerating functional verification with FPGA digital hard processor system is proposed. The proposed method combines the advantages of software simulation function verification and field programmable gate array prototype verification, and uses the hard processor system integrated in the on-chip system field programmable gate array device as the verification excitation generation and the function verification coverage analysis unit. It solves the problem that verification speed and flexibility can not be unified. Compared with software simulation verification, the proposed method can effectively shorten the functional verification time of digital circuits; it is superior to existing FPGA prototyping technology in terms of functional verification efficiency and verification of intellectual property reusability.