| 门控时钟技术在RTL功耗优化上的应用 |
| |
| 引用本文： | 孙大成,赵斌.门控时钟技术在RTL功耗优化上的应用[J].中国集成电路,2013(11):40-44. |
| |
| 作者姓名： | 孙大成 赵斌 |
| |
| 作者单位： | 中国电子科技集团公司第三十八研究所,合肥230088 |
| |
| 摘 要： | 本文简单介绍了门控时钟技术应用于RTL级功耗优化的原理.针对具体的RTL实例,利用门控时钟技术实现了RTL的功耗优化.实验结果表明：在采用门控时钟技术后,设计的功耗得到了显著降低,而代价则是增加很小的芯片面积.
|
| 关 键 词： | 门控时钟 功耗优化 |
RTL Level Power Optimization using Clock Gating |
| |
| SUN Da-cheng,ZHAO Bin.RTL Level Power Optimization using Clock Gating[J].China Integrated Circuit,2013(11):40-44. |
| |
| Authors: | SUN Da-cheng ZHAO Bin |
| |
| Institution: | (No.38 Research Institute, CETC, Hefei 230088, China) |
| |
| Abstract: | This paper briefly introduces the conception of RTL level power optimization using clock gating with specific designs as an example. We use Sequential Clock-Gating to optimize designs for power by discovering and implementing clock gating, to generate optimized RTL code. The experiment shows better results that the system＇ s power is significantly reduced after RTL power optimization with little chip area adding. |
| |
| Keywords: | clock gating power optimization |
| 本文献已被 维普 等数据库收录！ |
