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Characterizing slow state near Si-SiO2 in MOS structure
Authors:N Guenifi  D Bauza  R Mahamdi
Institution:1. LEA, Electronics Department, University of Mostefa Benboulaid Batna 2, Batna, Algeria;2. IMEP-LAHC, Minatec Grenoble, Franceguenifi_2000@yahoo.fr;4. IMEP-LAHC, Minatec Grenoble, France
Abstract:The Equilibrium Voltage Step (EVS) technique has been used for extraction of depth and energy concentration profile of traps situated in the oxide of a lightly stressed metal-oxide-semiconductor (MOS) structure. This has been achieved up to the very near Si-SiO2 interface. The results are discussed and compared with those obtained using charge pumping (CP) technique. A good agreement is achieved between the trap densities extracted using the two methods even though differences in the shape of the profiles can be observed. The results also very well agree with those published previously using current deep level transient spectroscopy (C-DLTS).
Keywords:Equilibrium Voltage Step (EVS)  characterization  Structure MOS
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