基于FPGA的32位除法器设计

介绍了一种使用可编程逻辑器件FPGA和VHDL语言实现32位除法器的设计方法。该除法器不仅可以实现有符号数运算，也可以实现无符号数的运算。除法器采用节省FPGA逻辑资源的时序方式设计，主要由移位、比较和减法三种操作构成。由于优化了程序结构，因此程序浅显易懂，算法简单，不需要分层次分模块进行。并使用Altera公司的QuartusⅡ软件对该除法器进行编译、仿真，得到了完全正确的结果。

Design of a 32-bit Divider Based on FPGA

This paper introduces a method of designing a 32-bit divider based on the programmable logic device FPGA and VHDL language. The divider can operate with sign decimal and unsign decimal. The divider is designed by timing sequence method which saves Les. Shifting, comparing and subtraction are main operations in the design. Because the program is optimized, the language is easy to read and understand. The arith- metic is simple and the division isn＇t achived by module and hiberarchy. Using Quartus 11 of Ahera, accurate compiling is carried out and waveforms are provided.