QDRⅡSRAM控制器研究及其应用

Xilinx FPGA内嵌的QDRII SRAM控制器实现了高速QDR协议，完成对QDRII SRAM的精确校正和高速数据的读写1]。基于内嵌QDRII SRAM控制器读/写状态机和物理接口设计的复杂性，本文详细论述了其实现的具体细节，包括burst2和burst4读写状态机的设计，物理接口读写通路的设计以及延迟校准的设计等。而且为了验证在系统环境下QDRII SRAM控制器的读写功能，本文设计了RapidIO到QDRII SRAM控制器的burst4接口，实现了带RapidIO接口的DSP、PowerPC等各类主机对于高速burst4 QDRII SRAM的读写访问。

Research and application of QDRII SRAM Controller

The Embedded QDRII SRAM Controller in Xilinx FPGA has realized high-speed QDR protocols,and completed precise calibration, read_write of high-speed data.For the complexity of designing read_write FSM and the physical layer interface of embedded QDRII SRAM Controller,this paper disscusses detaily about the specific details to realize it,such as the design of burst2 and burst4 read_write FSM, read_write path of physical layer, delay calibration and so on.In order to verificat the read_write fuction of QDRII SRAM Controller in the system environment, this paper gives the design of the QDRII SRAM interface access from RapidIO based on Xilinx FPGA and make the read_write access to high speed QDRII devices by a list of hosts with RapidIO interface.