| 基于Verilog的I^2C控制器的设计与综合 |
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| 引用本文： | 张文梅,刘伟,褚越强.基于Verilog的I^2C控制器的设计与综合[J].电子设计工程,2011,19(19):116-119,125. |
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| 作者姓名： | 张文梅 刘伟 褚越强 |
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| 作者单位： | 1. 中国人民解放军93756部队电子教研室,天津,300130
2. 北华航天工业学院,河北廊坊,065000 |
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| 摘 要： | 为满足嵌入式系统中专用芯片功能不能达到系统要求的现状．设计出一种功能可扩展的I^2C sLave控制器，这种控制器与传统的专用I^2C芯片不同。专用的I^2C片的功能具有固定性，只能实现一种或两种功能，而这种控制器是在FPGA上实现的。由于FPGA本身就具有可编程性，因此这种控制器也可以实现不同的功能，采满足在嵌入式系...
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| 关 键 词： | I^2C控制器 Verilog FPGA modelsim 状态机 |
Design and synthesis of I^2C controller based on verilog |
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| ZHANG Wen-mei,LIU Wei,CHU Yue-qiang.Design and synthesis of I^2C controller based on verilog[J].Electronic Design Engineering,2011,19(19):116-119,125. |
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| Authors: | ZHANG Wen-mei LIU Wei CHU Yue-qiang |
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| Institution: | 1.People’s Liberation Army Troops,Tianjin 300130,China; 2.North China Institute of Aerospace,Langfang 065000,China) |
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| Abstract: | Describe the FPGA, I^2C, Verilog basic concepts, together these three technologies design the I^2C slave controller on FPGA. The controller can receive data from the I^2C bus, it first determines whether the received address data match to their own address, If it matched and then analyze the received data, according to data received from the bus to control peripherals. Finally, in the preparation of testbaneh in modelsim simulation in I^2C bus to send data to the top of the I^2C slave controller module sends excitation signals to verify the correctness of the module. The results show that the controller module design is correct and has been designed to achieve the purpose ,which you can control the peripheral modules. |
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| Keywords: | I^2C controller Verilog FPGA modelsim state machine |
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