一种应用于GNSS接收机常数环路带宽的小数频率合成器

提出了一种应用于手持式民用GNSS接收机常数环路带宽的小数频率合成器，并在0.13μm 1P6M 的CMOS工艺中实现。通过离散的工作区域，LC-VCO用简单的结构获得宽的调节范围和小的压控灵敏度。提出的杂散抑制技术来最小化由于鉴频鉴相器和电荷泵引入的相位偏移。当PLL输出频率改变或温度变化时，通过自动环路校正模块自适应调整电荷泵电流保持优化的环路带宽不变。测试结果显示，该频率合成器带内相位噪声小于-93dBc（10 kHz 频率偏移处），杂散小于-70 dBc, 环路带宽变化小于?3%；在1V的电源供电下，整个合成器（不包括本振测试buffer）消耗4.5mA电流，面积为0.5mm2。

A constant loop bandwidth fractional-N frequency synthesizer for GNSS receivers

A constant loop bandwidth fractional-N frequency synthesizer for portable civilian global navigation satellite system (GNSS) receivers implemented in a 130 nm 1P6M CMOS process is introduced. Via discrete working regions, the LC-VCO obtains a wide tuning range with a simple structure and small VCO gain. Spur suppression technology is proposed to minimize the phase offset introduced by PFD and charge pumps. The optimized bandwidth is maintained by an auto loop calibration module to adjust the charge pump current when the PLL output frequency changes or the temperature varies. Measurement results show that this synthesizer attains an in-band phase noise lower than-93 dBc at a 10 kHz offset and a spur less than-70 dBc; the bandwidth varies by ±3% for all the GNSS signals. The whole synthesizer consumes 4.5 mA current from a 1 V supply, and its area (without the LO tested buffer) is 0.5 mm².