8GS/s-14bit RF-DAC中数字上变频器的ASIC实现

本文提出了一种内嵌于8GS/s-14bit RF-DAC中数字上变频器(DUC)的设计方案,该方案采用ASIC实现,能够得到采样频率达8 GHz的输出信号,并提供插值因子分别为2、4、8、16的上变频功能.基于CORDIC算法,提出16路时域交织的数控振荡器(NCO)结构,同时采用全半带滤波器(HB-FIR)折叠结构级联实现内插滤波器组.基于40 nm CMOS工艺,完成RTL级设计和GDSII版图设计,并将其内嵌于8 GS/s-14bit RF-DAC中完成混合SOC的电路设计与验证.测试结果显示,该设计可以在500 MHz的工作时钟频率下达到设计目标,数字部分的版图面积为2551*2580μm^2,仿真功耗约为1365.4 mW.在40 nm CMOS工艺下流片,流片测试结果显示该芯片设计能够完成预设目标,且在插值为16的模式下,测得芯片数字部分功耗为为1250 mW,符合设计预期.

ASIC implementation of digital upconverter in 8GS/s-14bit RF-DAC

This paper proposes a design scheme of digital upconverter(DUC)embedded in 8 GS/s-14 bit RF-DAC.The scheme is implemented by ASIC,which can get the output signal with sampling frequency up to 8 GHz and provide interpolation factors 2,4,8,16 upconversion function,respectively.Based on the CORDIC algorithm,a 16-channel time-domain interleaved numerically controlled oscillator(NCO)structure is proposed,and an interpolation filter set is realized by using a full half-band filter(HB-FIR)folding structure cascade.Based on the 40 nm CMOS process,the RTL-level design and GDSII layout design are completed and embedded in the 8 GS/s-14 bit RF-DAC to complete the circuit design and verification of the hybrid SOC.The test results show that the design can achieve the design goal at 500 MHz working clock frequency.The layout area of the digital part is 2551*2580μm^2,the simulation power consumption is about 1365.4 mW.And the film is tested in 40 nm CMOS process,The results show that the chip design can achieve the preset target,and in the mode of interpolation 16,the power consumption of the digital part of the chip is measured to be 1250 mW,which is in line with the design expectations.