| 准循环LDPC码低存储量译码器设计与实现 |
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| 引用本文： | 徐欢,雷菁,文磊.准循环LDPC码低存储量译码器设计与实现[J].重庆邮电学院学报(自然科学版),2010(6). |
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| 作者姓名： | 徐欢 雷菁 文磊 |
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| 作者单位： | 国防科技大学电子科学与工程学院; |
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| 摘 要： | 研究了准循环低密度奇偶校验(quasi-cyclic low density parity check,QC-LDPC)码及最小和译码算法,设计了合理的非均匀量化译码方案。充分利用准循环LDPC码校验矩阵的准循环结构特点,设计了一种低存储量准循环LDPC码的译码结构,详细描述各部分组成及功能。基于最小和译码算法及非均匀量化方案,给出了纠错性能的模拟测试结果。按照该译码结构在Xilinx公司的XC3S2000器件上实现了码长为9216、码率为1/2的准循环LDPC码译码器。FPGA(field programmable gate array)实现结果表明,与传统译码结构相比,该译码结构可节省约30%的存储空间,在性能与实现复杂度间取得了较好的平衡。
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| 关 键 词： | 准循环LDPC码 归一化最小和算法 现场可编程门阵列(FPGA)实现 |
Design and implementation of a memory efficient QC-LDPC code decoder |
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| XU Huan,LEI Jing,WEN Lei.Design and implementation of a memory efficient QC-LDPC code decoder[J].Journal of Chongqing University of Posts and Telecommunications(Natural Sciences Edition),2010(6). |
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| Authors: | XU Huan LEI Jing WEN Lei |
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| Institution: | XU Huan1,2,LEI Jing1,WEN Lei1(1.School of Electronic Science & Engineering,National University of Defense Technology,Changsha 410073,P.R.China,2.Mailbox 21 Ext.187,Urumchi 841700,P.R.China) |
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| Abstract: | This paper studied the QC-LDPC(quasi-cyclic low density parity check) codes and min-sum decoding algorithm,and designed a proper ununiform decoding scheme for quantization.According to the structure of parity check matrix of QC-LDPC code,a decoder architecture was designed,with its components and function discussed in detail.According the decoding algorithm and quantization scheme,simulated error correcting performance was made.A QC-LDPC decoder was implemented in Xilinx XC3S2000 FPGA(field programmable gat... |
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| Keywords: | QC-LDPC code normalized min-sum algorithm FPGA(field programmable gate array) implement |
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