A method for partitioning applications in hybrid reconfigurable architectures |
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Authors: | Email author" target="_blank">Michalis?D?GalanisEmail author Athanasios?Milidonis George?Theodoridis Dimitrios?Soudris Costas?E?Goutis |
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Institution: | (1) VLSI Design Lab., Elect. & Comp. Eng. Dept., University of Patras, Greece;(2) Section of Elect. & Computers, Physics Dept., Aristotle University, Thessalonica, Greece;(3) VLSI Design Center, Elect. & Comp. Eng Dept., Democritus University, Xanthi, Greece |
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Abstract: | In this paper, we propose a methodology for accelerating application segments by partitioning them between reconfigurable
hardware blocks of different granularity. Critical parts are speeded-up on the coarse-grain reconfigurable hardware for meeting
the timing requirements of application code mapped on the reconfigurable logic. The reconfigurable processing units are embedded
in a generic hybrid system architecture which can model a large number of existing heterogeneous reconfigurable platforms.
The fine-grain reconfigurable logic is realized by an FPGA unit, while the coarse-grain reconfigurable hardware by our developed
high-performance data-path. The methodology mainly consists of three stages; the analysis, the mapping of the application
parts onto fine and coarse-grain reconfigurable hardware, and the partitioning engine. A prototype software framework realizes
the partitioning flow. In this work, the methodology is validated using five real-life applications. Analytical partitioning
experiments show that the speedup relative to the all-FPGA mapping solution ranges from 1.5 to 4.0, while the specified timing
constraints are satisfied for all the applications. |
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Keywords: | Hybrid reconfigurable systems Partitioning Coarse-grain reconfigurable hardware FPGA scheduling |
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