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Verification of submodeling technique in thermomechanical reliability assessment of flip-chip package assembly
Authors:Yi-Shao Lai  Tong Hong Wang
Institution:Stress-Reliability Laboratory, Advanced Semiconductor Engineering, Inc., 26 Chin 3rd Rd., Nantze Export Processing Zone, 811 Nantze, Kaohsiung, Taiwan
Abstract:In this paper we verified the submodeling technique applied in the thermomechanical reliability assessment of a flip-chip BGA under accelerated thermal cycling test conditions. Since the steady-state creep model was implemented for the solder bump to better represent its realistic mechanical behavior, submodeling procedures developed specifically for path-dependent thermomechanical problems were considered. A detailed global model for the flip-chip BGA was built up to verify submodeling solutions. This model also served as a benchmark to examine solution discrepancies caused by different simplifications of the global model.
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