A Strong Anti-Jamming Algorithm Based on FPGA for Estimating Loop Delay in Digital Predistortion System

At present what are the key points focused in the research of loop-delay estimation for the digital predistorter in the radio frequency (RF) power amplifier system is reducing its complexity of engineering realization and improving anti-jamming ability and computational speed. Besides, opening up its application scope should be contained. For these targets, a novel method including integer loop delay estimation and fractional part is proposed. The integer part applies amplitude-difference summation function and the fractional one adopts the method of finite impulse response (FIR) linear interpolation. The algorithm finds wide applications. What is more, strong anti-jamming ability and low complexity are also its merits. Simulation results support the above opinion. Digital predistortion (DPD) system based on this algorithm achieves good performance.