Memory effect in MIS structures with amorphous silicon nanoparticles embedded in ultra thin SiOx matrix

Metal/${\mathrm{SiO}}_2$/a-Si-${\mathrm{SiO}}_x$/c-Si structures containing amorphous silicon nanoparticles (a-Si NPs) embedded in ultra thin ${\mathrm{SiO}}_x$ matrix are fabricated by thermal evaporation of ${\mathrm{SiO}}_x$ and sputtering of ${\mathrm{SiO}}_2$ layers followed by thermal annealing at $700{}^{\circ }\mathrm{C}$. A memory effect, due to charging of a-Si NPs in ${\mathrm{SiO}}_x$, is observed. The processes of NP charging and discharging are accomplished by applying pulses with alternative polarities. The observed shift of the flat band voltage of the high-frequency C–V curve caused by a voltage pulse of $-15\mathrm{V}$ having duration of 1 s is more than 3 V. In addition, the structures show good retention characteristics which make them promising for application in non-volatile memory devices.