| 一种用于半并行A/D转换器的比较器设计 |
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| 引用本文： | 徐鸣远,周述涛,朱璨,沈晓峰.一种用于半并行A/D转换器的比较器设计[J].微电子学,2010,40(2). |
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| 作者姓名： | 徐鸣远 周述涛 朱璨 沈晓峰 |
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| 作者单位： | 中国电子科技集团公司,第二十四研究所,重庆,400060;模拟集成电路国家级重点实验室,重庆,400060 |
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| 摘 要： | 简要介绍了半并行结构的A/D转换器原理。针对该结构的A/D转换器,提出了一种能自动校零、迟滞、全差分输入及多级前置放大的比较器。解决了输入失调电压、噪声环境下单转换、电荷注入、带宽、转换速度等问题。给出了应用该比较器的0.6μm CMOS半并行A/D转换器的性能。结果表明,设计的比较器能使丰并行ADC的DNL和INL小于±0.5 LSB,SNR大于48dB。
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| 关 键 词： | 半并行 A/D转换器 自动校零 迟滞比较器 |
Design of a Comparator for Half-Flash A/D Converter |
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| XU Mingyuan,ZHOU Shutao,ZHU Can,SHEN Xiaofeng.Design of a Comparator for Half-Flash A/D Converter[J].Microelectronics,2010,40(2). |
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| Authors: | XU Mingyuan ZHOU Shutao ZHU Can SHEN Xiaofeng |
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| Institution: | Sichuan Institute of Solid-State Circuits/a>;CETC/a>;Chongqing 400060/a>;P.R.Chnia/a>;National Laboratory of Analog Integrated Circuits/a>;P.R.Chnia |
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| Abstract: | Theory of operation of A/D converter with half-flash structure was described. A multi-stage pre-amp comparator with auto-zero, hysteresis and fully differential input was proposed for half-flash A/D converter. Problems of input offset voltage, single conversion in noise environment, charge injection, bandwidth and conversion rate were solved. A half-flash A/D converter was fabricated in 0.6 μm CMOS process. Test results showed that the A/D converter had a DNL/INL less than ±0.5 LSB and an SNR more than 48 dB. |
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| Keywords: | Half-flash A/D converter Auto-zero Hysteretic comparator |
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