一种适合于SOC系统的JTAG扩展化可测性设计

随着集成电路系统复杂性的提高及基于 IP核的 SOC系统的出现 ,电路测试的难度不断增大 ,对电路可测性设计提出了更高的要求。文中在研究了现有各种可测性设计方法优劣后提出了扩展化的 JTAG可测性设计电路 ,它在稍增加电路复杂度的情况下融合各测试方法 ,并提出了利用这种测试电路的 IC系统测试方案。它克服了测试基于 IP核的 SOC系统的一些难点。

A JTAG Standard-based Test Circuit Design for SOC System

Along with the more complicated integrated circuit system and the emergence of IP-based SOC system, the test of IC system becomes more difficult and faces new challenge. In this paper we design a JTAG-based test circuit design after studying some important kinds of test techniques. It embraces some different test techniques at the little cost of the circuit complexity and overcomes some difficult issues in the test of IP-bases SOC system. We also give the test strategy based on this circuit.