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3-D electrothermal simulation of active cycling on smart power MOSFETs during short-circuit and UIS conditions
Institution:1. Department of Electrical Engineering and Information Technology, University Federico II, via Claudio 21, 80125 Naples, Italy;2. SATIE, CNAM, CNRS, ENS Cachan, 61 Av. du Président Wilson, 94234 Cachan, France;3. Université Paris-Est Créteil Val de Marne, 61 avenue du Général de Gaulle, 94010 Créteil Cedex, France;4. Freescale Semiconductor, Avenue du Général Eisenhower, 31023 Toulouse, France;1. Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona, Cerdanyola del Valles, Spain;2. Departamento de Electricidad y Electrónica, Universidad de Valladolid, Valladolid, Spain;3. Department of Chemistry, University of Helsinki, Helsinki, Finland;1. Engineering Product Development Pillar, Singapore University of Technology and Design, Singapore 138 682, Singapore;2. Department of Mechanical Engineering, Massachusetts Institute of Technology, Cambridge, MA 02139, USA;1. STMicroelectronics, 850, rue Jean Monnet, 38926 Crolles Cedex, France;2. Laboratory of Computer Sciences, Paris 6 (LIP6), Systems On Chips Department, UPMC University, 4 place Jussieu, 75252 Paris Cedex 05, France;1. Le2i, UMR CNRS 6306, University of Burgundy, 9 Avenue Alain Savary, 21000 Dijon, France;2. Centre National d’Etudes Spatiales (CNES), 18 Avenue Edouard Belin, 31401 Toulouse, France;1. IMS-Bordeaux, Université de Bordeaux – UMR 5218, 351 cours de la Libération, 33405 Talence, France;2. Information Technology Laboratory, Gottfried Wilhelm Leibniz Universität Hannover, Hannover, Germany
Abstract:Active cycling of power devices operated in harsh conditions causes high power dissipation, resulting in critical electrothermal and thermo-mechanical effects that may lead to catastrophic failures. This paper analyzes the ageing-induced degradation of the chip metallization of a power MOSFET and its impact on the device robustness during short-circuit and unclamped inductive switching tests. A 3-D electrothermal simulator relying on a full circuit representation of the whole device is used to predict the influence of various ageing levels. It is found that ageing can jeopardize the robustness of the transistor when subject to short-circuit conditions due to the exacerbated de-biasing effect on the gate-source voltage distribution; conversely, this mechanism does not arise under unclamped inductive switching conditions. This allows explaining the difference in time-to-failure experimentally observed for the transistors subject to these tests and dissipating the same energy.
Keywords:Active cycling  Ageing effects  Electrothermal simulation  Short circuit test  Power MOSFETs  Unclamped inductive switching
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